Abstract: A semiconductor integrated circuit device includes a first delay circuit delaying a first clock signal, a second delay circuit delaying a second clock signal which has an inverted phase with respect to the first clock signal, a phase comparator outputting a phase error signal based on a comparison of the first clock signal and a feedback signal corresponding to an output signal from the first delay circuit, a delay control circuit generating a delay control signal based on the phase error signal, for variably controlling a delay quantity of the first and second delay circuits, and a timing adjusting circuit variably controlling a delay quantity of the second delay circuit by supplying the delay control signal to the second delay circuit at a timing synchronized to the second clock signal.

Abstract: Heatsink structures for integrated circuit chips, chip packages, printed wiring boards and the like are disclosed. The heatsink structures according to the present invention have thin flexible cooling fins which move and vibrate under the flow of a cooling fluid. In one embodiment, the fins comprise a thin metal film, such as copper or aluminum, which is laminated to a thin polymeric layer. The polymeric layer provides resilience and elasticity to the metal film and the cooling fins.

Abstract: It is one aspect of the present invention to split a common data bus established in common for a plurality of segments into a read-dedicated common data bus and a write dedicated common data bus, in a memory device comprising a plurality of segments each of which includes a plurality of memory cells. With such a constitution, write data can be supplied to the write data bus even when read data are present on the read common data bus due to a read operation; and even when operation frequencies increase, there are no limitations to the timing of write operations following reading and the speed of write operations following reading can be increased.

Abstract: In a first UPC, a PCR is set as a monitor rate for each connection. If a transfer rate of a cell exceeds the PCR set for the connection, the cell is discarded. In a second UPC, an ACR is set as a monitor rate for each connection. If the transfer rate of the cell exceeds the ACR set for the connection, a lower priority is assigned to that cell. Additionally, with a configuration where one UPC monitors a varying rate, a parameter change process is controlled by obtaining a time between a passage time of a detected B-RM cell and an arrival of a user cell and comparing the obtained time with maximum and minimum delay standard values. A parameter table including some parameters is provided. A header of an arrived cell in a forward direction is extracted, and it is determined whether or not the arrived cell is a violation cell using the leaky bucket algorithm, etc. If the arrived cell is a violation cell, it is discarded.

Abstract: A meter-rate billing system is disclosed in which billing is performed according to an interval while a subscriber uses a network actually, without any exclusive device. The meter-rate billing system on a LAN system for controlling connections to other networks includes a table in which a subscriber information is registered, a LAN controller for retrieving the table according to said subscriber information when a subscriber accesses joining to said LAN system accesses the LAN system, registering the subscriber information in said table if the information has not been registered, updating the registration information if the subscriber information is registered, and deleting the registration information if the registration information is not updated within a predetermined interval, and a billing device for receiving the registration information stored in the table in every predetermined informing interval and judging an interval time during which the registration information is registered in the table.

Abstract: A semiconductor device manufacturing method where the first insulating film, the first semiconductor film, and the second insulating film are formed in sequence on or above a semiconductor substrate. A resist mask having a window therein is formed on the second insulating film. A first hole is formed in the second insulating film via the window or the first hole is formed in the second insulating film and the first semiconductor film. An overetching using a halogen compound gas forms a sidewall on an inner peripheral surface of the first hole. A second hole having a small diameter than the first hole is formed by etching through the first hole surrounded by the sidewall and the resist.

Abstract: A semiconductor device having multiple circuit elements capable of performing different functions and that operate at a high frequency includes island regions on which the circuit elements are located and isolation regions that surround the island regions and thus, the circuit elements. The island regions electrically separate the circuit elements from each other. A capacitor is connected between a substrate portion of the semiconductor device and ground. The isolation regions include a conductive region with a conductivity type opposite to the conductivity type of the substrate portion, such that a parasitic capacitor is formed between the substrate portion and the conductive region. The parasitic capacitor prevents signal leakage between the circuit elements and the island regions.

Abstract: An optical device, such an as optical circulator or switch, which includes a birefringent tapered element, such as a birefringent wedge, positioned between first and second Faraday rotators. Light travels through the first Faraday rotator, the first birefringent tapered element and then the second Faraday rotator, in order, and along travel paths which are not parallel to each other.

Abstract: An information searching apparatus converts an input key-term into key-terms for searching the database by at least two times of expansions using a related-term dictionary and a translation dictionary, and stores the history of the expansions in the form of a tree structure. Then, a part or the whole of the thus-stored tree structure is displayed on a screen. A searcher designates appropriate terms among the thus-displayed information as key-terms for searching.

Abstract: A circuit element placement method and apparatus in which circuit elements can surely be placed in a short time even if a circuit scale is increased. For this purpose, there is sequentially executed a first step of determining placement coordinates of sequential logic circuit elements among many circuit elements to be placed and a second step of determining placement coordinates of circuit elements other than the sequential logic circuit elements with consideration given to the placement coordinates of the sequential logic circuit elements, determined in the first step. The method and apparatus are applicable at a time of design of an integrated circuit such as LSI, or a circuit on a printed wiring board.

Abstract: A ruled line extracting apparatus obtains circumscribed rectangles of pixel concatenation regions included in an input pattern, and calculates the most frequent value of their heights. Additionally, the apparatus integrates segments by ignoring a wild card segment, and calculates the most frequent value of height/width of extracted straight lines and segments structuring the straight line. Next, it performs a process for integrating/deleting straight lines using each threshold value based on the highest frequency value. Then, it checks/deletes a straight line according to a distribution of black pixels around the straight line, and recognizes the remaining straight lines as ruled line candidates.

Abstract: An ATM cell multiplexer is arranged so that in the up direction from the terminal equipments/ATM cell interfaces to the ATM switchboard the ATM bus scheduler allocates the transmission rights for each CLAD unit in accordance with a preset schedule table and predetermined service categories or traffic control for the transmission of cells, and in the down direction from the ATM switchboard to the terminal equipments/ATM cell interfaces the cells are broadcast to all of the CLAD units which decide for the reception of the cells as to whether or not the cells are addressed to themselves.

Abstract: Several inventive features for increasing the yield of substrate capacitors are disclosed. The inventive features relating to selective placement of insulating layers and patches around selected areas of the capacitor's main dielectric layer. These insulating layers and defects prevent certain manufacturing processing steps from creating pin-hole defects in the main dielectric layer. The inventive features are suitable for any type of material for the main dielectric layer, and are particularly suited to anodized dielectric layers.

Abstract: The present invention relates to a heat dissipation structure for a notebook type computer, capable of effectively dissipating heat generated from a high temperature element (such as a CPU). The heat dissipation structure comprises a main body, a display device and a hinge shaft for coupling the main body with the display device, wherein the hinge shaft is arranged above the main body at a distance therefrom, and a heat dissipation means is provided in the main body.

Abstract: An E-mail distributing system which is composed of a server and a client including a user, and distributes an E-mail corresponding to a group including a plurality of clients. The client transmits a mail acquisition demand including a group identifier, and the server includes personal mail spools and group mail spools. The received E-mails are accumulated in the mail spools according to an arrival address. When a mail acquisition demand from the client includes the group identifier, the E-mail with top priority corresponding to the group identifier is extracted from the group mail spools and is then distributed to the client.

Abstract: A gate insulating film is formed on the surface of active regions of a semiconductor substrate, and a first polysilicon film is deposited on the semiconductor substrate. Impurities are selectively doped into the first silicon film in an area where a capacitor is to be formed. A dielectric film is formed on the first silicon film. A second silicon film doped with impurities is formed on the dielectric film. The second silicon film and dielectric film are patterned so that the second silicon film and dielectric film are left in the area where the capacitor is to be formed, and not left in the area where MISFET are to be formed. A third silicon film is deposited on the whole surface of the substrate.

Abstract: A reference voltage generation circuit includes: a load unit having one end thereof connected to a higher voltage power supply line; an enhancement type n-channel MIS transistor having a drain thereof connected to the other end of the load unit, and a source thereof connected to a lower voltage power supply line; and a source follower circuit using a MIS transistor has a driving element, the source follower circuit having an input end thereof connected to the drain of the n-channel MIS transistor and having an output end thereof connected to a gate of the n-channel MIS transistor. A reference voltage is obtained at the drain of the n-channel MIS transistor. By the constitution, it is possible to obtain a stable reference voltage, and to incorporate the reference voltage generation circuit into an integrated circuit produced by integrating MIS transistors, without introducing an increase in production processes. It is also possible to reduce a consumed current of the reference voltage generation circuit.

Abstract: A magneto-optical recording medium capable of perfectly masking a mark adjacent to a mark to be reproduced to thereby improve a reproduction output. The magneto-optical recording medium includes a transparent substrate, a magnetic reproducing layer laminated on the transparent substrate, a nonmagnetic intermediate layer laminated on the magnetic reproducing layer, and a magnetic recording layer laminated on the nonmagnetic intermediate layer. The reproducing layer has an easy direction of magnetization in a plane at room temperature, and has an easy direction of magnetization perpendicular to a film surface at a given temperature or higher. The nonmagnetic intermediate layer is thin enough to allow magnetostatic bond between the recording layer and the reproducing layer at the given temperature or higher.

Abstract: A pen-input information processing device comprises a pen housing for housing a pen, a processing device, a suspension/resumption-instruction-unit for instructing the processing device to perform state transition, from a suspended state to a normal state and vice versa, a pen-housing-detection-unit which outputs a pen-housing-detection-signal which shows the existence or non-existence of a pen in the pen housing in detecting the housing of the pen in the pen housing, and a state-transition-control-unit which generates a state-transition-control-signal which instructs the processing device to perform the transition of a state unconditionally when the suspension/resumption-instruction-unit instructs the processing device to perform the state transition, or does not instruct the processing device to perform state transition in either case where a state is in the suspended state and also the pen-housing-detection-signal shows the housed state of the pen in the pen housing, or where the state is in the normal stat