Patents Assigned to Fujitsu
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Publication number: 20010001261Abstract: A semiconductor memory, such as an SDRAM, includes a data bus pair, a first reset circuit, a second reset circuit and a control circuit. The first reset circuit is connected between the buses of the data bus pair and resets the buses at a first potential. The second reset circuit is also connected between the data buses and resets the buses at a second potential. The control circuit is connected to the first and second reset circuits and activates the first reset circuit and deactivates the second reset circuit prior to a write operation. The control circuit further deactivates the first reset circuit and activates the second reset circuit prior to a read operation.Type: ApplicationFiled: January 10, 2001Publication date: May 17, 2001Applicant: FUJITSU LIMITEDInventors: Hiroyuki Sugamoto, Takaaki Furuyama
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Patent number: 6233348Abstract: A feature point information calculating unit calculates the connection of a feature point extracted by a feature point extracting unit through a ridge. An identifying unit identifies the connection state of the feature point calculated by the feature point information calculating unit.Type: GrantFiled: March 23, 1998Date of Patent: May 15, 2001Assignee: Fujitsu LimitedInventors: Yusaku Fujii, Takashi Shinzaki, Ken Yokoyama
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Patent number: 6232051Abstract: The resist to be used for the method of this invention in producing a semiconductor device is patterned by a procedure which comprises the steps of disposing in the direction of a semiconductor wafer a first mask having circuit patterns repeatedly formed at a plurality of positions, then shielding those of said plurality of circuit patterns which overlap the edge of the semiconductor wafer with a blind to an extent such that the remaining circuit patterns are not shielded, exposing a resist overlying the semiconductor wafer by using the first mask held in a state partially shielded by the blind, projecting light through a second mask provided with a light passing pattern defined by a shielding film to an area of the resist to which the edge of the blind is transferred, and developing the resistType: GrantFiled: July 29, 1998Date of Patent: May 15, 2001Assignee: Fujitsu LimitedInventor: Kazuaki Suzuki
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Patent number: 6232998Abstract: A printing apparatus for printing on double-sides of a recording medium has a first print control unit for controlling an one-line exposure for the right or reverse side by a horizontal synchronous signal, and a second print control unit for controlling the one-line exposure for the reverse or right side by using this horizontal synchronous signal. A print start timing for the right side can be synchronized with a timing for the reverse side, and is capable of preventing a deviation in print position between the right side and the reverse side of the recording medium even by providing the print control units for the right side and the reverse side, individually.Type: GrantFiled: April 6, 1999Date of Patent: May 15, 2001Assignee: Fujitsu LimitedInventors: Motohiro Tokairin, Amiko Chihara, Yoshinori Wada
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Patent number: 6233701Abstract: A test program execution control apparatus, in which an operation of testing is started according to controls by a test program execution control section, a period of editing data for test results to a test editing section is specified by an editing period input section, the data for test results within the editing period is edited by a test result editing section, an order of execution of testing for test items to be executed as a test program and whether testing is executed or not are decided from the results of editing by a test item scheduling section, a test-item execution table is prepared depending on the order of execution of testing for the decided test items as well as on the condition as to whether testing thereto is executed or not, and the test program is discretely executed for each test item according to the contents of the test-item execution table.Type: GrantFiled: September 25, 1998Date of Patent: May 15, 2001Assignee: Fujitsu LimitedInventor: Kunihito Onoue
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Patent number: 6233076Abstract: When a branching unit combines a first optical signal transmitted from a branch station with a second optical signal which is different in power level from the first optical signal and is transmitted from a terminal station A or B in an optical add-drop system, the S/N ratio of the lower power level of the two different power levels decreases, thereby deteriorating the system performance. Therefore, a dummy light is transmitted together with an optical signal to adjust the power level of the optical signal. Otherwise, an optical attenuator or an active optical signal level adjustment unit is provided for the branching unit so that both optical signals to be combined can be equal in level.Type: GrantFiled: September 5, 1997Date of Patent: May 15, 2001Assignee: Fujitsu LimitedInventors: Hiroyuki Iwata, Shinichirou Harasawa
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Patent number: 6232724Abstract: An LED array composed of a plurality of LEDs is disposed on either side of a signal interconnection board, while metal plates are disposed on the other side of the signal interconnection board as positive and negative power source lines for driving the LEDs, respectively, and a capacitor is provided between the positive metal plate for power supply and the negative metal plate for power supply. As a result, the LED array in which an output light is not lowered in power, no variations in light output arises in every LEDs, and all the LEDs can be turned on simultaneously is provided.Type: GrantFiled: December 23, 1998Date of Patent: May 15, 2001Assignees: Fujitsu Limited, Hitachi Cable Ltd.Inventors: Takashi Onimoto, Hideo Tanaka, Tamotsu Nishiura
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Patent number: 6233240Abstract: A system and method for performing event-based rate policing using varying window start times. Rate policing overhead, including counter and timer monitoring and resetting, is performed only as needed and in response to actual received traffic on each connection. As the last bit of a data unit is received from an external network, an “event time stamp” is generated and associated with the data unit, for example as part of an internal header or trailer attached to the data unit. To determine if a rate policing window was active when the frame was received, the event time stamp is compared with a sum of a window start time and a window period value stored in association with the connection on which the data unit was received. If the associated event time stamp indicates a time prior to the sum of the associated window start time and window period, then a rate policing window is determined to have been active when the frame was received.Type: GrantFiled: October 26, 1999Date of Patent: May 15, 2001Assignee: Fujitsu Network Communications, Inc.Inventors: Steve N. Barbas, Michael J. Homberg
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Patent number: 6233145Abstract: A function of the extending apparatus for an information processing device including at least one connector provided on a surface of the function extending apparatus for mounting the information processing device, and connected with a corresponding connector provided on a lower surface of the information processing device, when the information processing device is mounted on the function extending apparatus. The function extending apparatus includes a pushing member moved in an upper direction so as to push the information processing device up from the function extending apparatus, a rotatable operation member, and a push-up mechanism which moves the pushing member in the upper direction, when the operation member is rotated.Type: GrantFiled: March 21, 2000Date of Patent: May 15, 2001Assignee: Fujitsu LimitedInventor: Masuo Ohnishi
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Patent number: 6232816Abstract: A signal level monitoring circuit for outputting either voltage or current corresponding to an input signal level, includes a variable gain unit for obtaining a predetermined output level without being dependent on a gain, when the input signal level is a predetermined reference input level; and an offset adding unit for outputting a predetermined reference output level by adding an offset level to the output level of the variable gain means, when the input signal level is the predetermined reference input level. According to the present invention, it is possible to adjust precisely and surely the gain and the offset voltage based on simple adjusting steps in a short time and only once.Type: GrantFiled: August 25, 1998Date of Patent: May 15, 2001Assignee: Fujitsu LimitedInventor: Tomio Ueda
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Patent number: 6231158Abstract: The present invention relates to an ink jet printer in which drops of ink are jetted out onto a surface of a recording medium so as to record an image. The present invention is to obtain an economical ink jet printer in which a reaction force generated in the reciprocal motion of the ink jet head is simply canceled, and the ink jet printer is small and light, and less vibration is caused in the printer, and further it is possible to drive the printer with a small amount of drive energy.Type: GrantFiled: July 13, 1995Date of Patent: May 15, 2001Assignee: Fujitsu LimitedInventors: Masao Hiyane, Toshio Fukushima, Kazuki Ogawa, Yasuo Numata, Yuji Yoshida
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Patent number: 6233732Abstract: A compiling system includes a first unit for converting a source program into an intermediate text formed of intermediate codes, each of the intermediate codes having a portion used to explicitly indicate information regarding a state of computer hardware, the computer hardware being operated in accordance with a machine language program, and a second unit for generating a machine language program using the intermediate codes of the intermediate text. In addition, a compiling system includes a first unit for converting a source program into an intermediate text formed of intermediate codes, each of the intermediate codes having a portion used to define a plurality of values, and a second unit for generating a machine language program using the intermediate codes of the intermediate text.Type: GrantFiled: November 12, 1996Date of Patent: May 15, 2001Assignee: Fujitsu LimitedInventors: Manabu Matsuyama, Yutaka Igarashi, KohIchiro Hotta, Masakazu Hayashi
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Patent number: 6232664Abstract: An interlayer insulation film is formed on a semiconductor substrate. A wiring is formed on a part of the surface area of the interlayer insulation film. This wiring has a laminated structure including two or more layers. That is, the wiring includes an underlayer or a first conductive layer which is made of Ta in an a phase, and an overlayer or a second conductive layer which is made of an Al alloy.Type: GrantFiled: January 8, 1999Date of Patent: May 15, 2001Assignee: Fujitsu LimitedInventor: Takahiro Kono
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Patent number: 6233520Abstract: There is provided a map data access method and device capable of reading out from a recording medium the map data requested by a navigation system and providing them to the system whether C language, etc. or JAVA (trademark), etc. is employed to constitute a processing program on the navigation system side. In the recording medium, the map data and a reading method of the data are recorded in pairs in a map data section and a method section, respectively. When a navigation function section requests the map data, a data access section reads out desired data in a method (program) read out from the method section according to a requested application programming interface (API). The data read out are supplied as a byte array object to the navigation function section.Type: GrantFiled: February 12, 1999Date of Patent: May 15, 2001Assignees: Toyota Jidosha Kabushiki Kaisha, Aisin AW Co., Ltd., Denso Corporation, Fujitsu Ten Limited, Matsushita Electric IndustrialInventors: Toru Ito, Akimasa Nanba, Hidetoshi Fujimoto, Hiroshi Takeuchi, Fumihiko Matsumura, Nobuyuki Nakano
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Patent number: 6232147Abstract: A semiconductor device equipped with secondary pads having adequate arrangement for an arbitrary packaging process. The secondary pads are connected with the primary pads of the semiconductor device with a novel lead wire structure, which is characterized by its low electric resistance, good mechanical strength to protect active components of the device, good adhesion to bumps, and anti-electromigration property.Type: GrantFiled: August 2, 1999Date of Patent: May 15, 2001Assignee: Fujitsu LimitedInventors: Hirohisa Matsuki, Kenichi Kado, Eiji Watanabe, Kazuyuki Imamura, Takahiro Yurino
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Patent number: 6230562Abstract: A detection circuit for a vibratory gyro includes a first circuit which detects a detection signal output from the vibratory gyro and produces an output signal indicative of an angular velocity applied to the vibratory gyro, and a second circuit which is operatively coupled to the first circuit and reduces a leakage component included in the detection signal.Type: GrantFiled: March 11, 1997Date of Patent: May 15, 2001Assignees: Fujitsu Limited, Fujitsu Towa Electron LimitedInventors: Hiroshi Ishikawa, Masanori Yachi, Sumio Yamada, Yoshitaka Takahashi, Yoshio Satoh
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Patent number: 6232554Abstract: A cable entrance module is provided at a position of equipment at which a cable enters the equipment from the outside. The cable is inserted through the inside of the cable entrance module. The cable entrance module includes an entrance-side membrane, an exit-side membrane, and a viscous-matter-filling portion. The inside of the filling portion is filled with viscous matter. The entrance-side membrane has such strength that when it is pierced by the extending end of the cable it is pushed by the extending end of the cable. The exit-side membrane has a strength such that it is not pierced by the viscous matter when the cable pierces the entrance-side membrane, enters the viscous-matter filling portion, and moves through the viscous matter in the viscous-matter filling portion while pushing the viscous matter aside. The exit-side membrane is pierced by the extending end of the cable when it is pushed by the extending end of the cable.Type: GrantFiled: April 23, 1999Date of Patent: May 15, 2001Assignee: Fujitsu LimitedInventors: Naoya Yamazaki, Motoko Nakamura
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Patent number: 6232663Abstract: A semiconductor device and a method of fabricating thereof, including an insulator layer having alternately layered insulator films and boundary layers, wherein the boundary layers are more dense than the insulator films to prevent expansion and elongation of string-like defects across the boundary layers. The method includes mixing a nitrogen containing gas and a silane group gas to form an insulator film; temporarily stopping a flow of the silane group gas for approximately one to fifteen seconds to form a boundary layer over the insulator film; restarting the flow of the silane group gas; and repeating the steps of temporarily stopping and restarting for a predetermined number of times to form the plurality of alternately layered insulator films and boundary layers. The plurality of alternately layered insulator films and boundary layers is also etched at an etching rate for the insulator films greater than an etching rate for the boundary layers to form a step-shaped sloped opening.Type: GrantFiled: August 1, 1997Date of Patent: May 15, 2001Assignees: Fujitsu Limited, Advanced Micro Devices, Inc., Fujitsu AMD, Semiconductor LimitedInventors: Toshio Taniguchi, Kenji Nukui, Ibrahim Burki, Richard Huang, Simon Chan, Kazunori Imaoka, Kazutoshi Mochizuki
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Publication number: 20010000853Abstract: A tuning-fork vibratory gyro has first and second arms and a base integrally connected to the first and second arms. The gyro includes drive electrodes used to generate tuning-fork vibrations due to a piezoelectric transversal effect, and detection electrodes provided on the first and second arms and used to output a detection voltage due to an angular velocity.Type: ApplicationFiled: December 22, 2000Publication date: May 10, 2001Applicant: FUJITSU LIMITEDInventors: Masanori Yachi, Yoshio Satoh, Masaaki Ono, Yoshiro Fujiwara, Sumio Yamada, Hiroshi Ishikawa
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Publication number: 20010000994Abstract: A semiconductor device which receives addresses in synchronism with a clock signal and receives data in synchronism with a strobe signal includes address-latch circuits, a first control circuit which selects one of the address-latch circuits in sequence in response to the clock signal, and controls the selected one of the address-latch circuits to latch a corresponding one of the addresses in response to the clock signal, and a second control circuit which selects one of the address-latch circuits in sequence in response to the strobe signal, and controls the selected one of the address-latch circuits to output a corresponding one of the addresses in response to the strobe signal.Type: ApplicationFiled: December 12, 2000Publication date: May 10, 2001Applicant: Fujitsu LimitedInventors: Hiroyoshi Tomita, Tatsuya Kanda