Patents Assigned to Global Unichip Corporation
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Patent number: 12292850Abstract: A die-to-die communication system and an operation method thereof are provided. The die-to-die communication system includes a transmitting device disposed at a first die and a receiving device disposed at a second die, wherein the first die and second die are disposed in a same integrated circuit package. The receiving device is coupled to the transmitting device via a communication interface. The transmitting device transmits a data unit stream to a data channel in the communication interface. The receiving device receives the data unit stream from the data channel in the communication interface. The receiving device returns transmission management information to the transmitting device via a feedback channel different from the data channel in the communication interface. In various embodiments, the transmission management information includes flow control information and/or error replay information.Type: GrantFiled: May 23, 2023Date of Patent: May 6, 2025Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Sheng Fang, Igor Elkanovich, Pei Yu
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Patent number: 12283957Abstract: An interface device and a signal transceiving method thereof are provided. The interface device includes a slave circuit and a master circuit. The slave circuit is coupled to the master circuit and includes a first programmable delay line, a first output clock generator, and a first phase detector. The first programmable delay line provides a first adjusting delay amount according to a first adjust signal, and generates a first delayed clock signal by delaying a first clock signal according to the first adjusting delay amount. The first output clock generator generates a second clock signal according to the first delayed clock signal. The first phase detector detects a phase difference of the first clock signal and the second clock signal to generate first phase lead or lag information. The first adjust signal is generated according to the first phase lead or lag information.Type: GrantFiled: August 31, 2022Date of Patent: April 22, 2025Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bi-Yang Li, Igor Elkanovich, Hung-Yi Chang, Shih-Cheng Kao
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Patent number: 12235717Abstract: A communication system and an operation method thereof are provided. A transmitting device transmits a data unit to a receiving device through a data channel of a communication interface. The transmitting device calculates an original verification information unit of the data unit and synchronously transmits the original verification information unit to the receiving device through a verification information channel of the communication interface based on a transmission timing of the data unit in the data channel. After receiving a current data unit and before receiving a next data unit, the receiving device verifies whether the current data unit received from the data channel has errors in real time based on a current original verification information unit corresponding to the current data unit.Type: GrantFiled: November 8, 2022Date of Patent: February 25, 2025Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Igor Elkanovich, Yung-Sheng Fang, Pei Yu, Chang-Ming Liu
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Publication number: 20250015939Abstract: The disclosure provides a communication system between dies and a repairing method for lanes between dies. The communication system includes a transmitting device disposed on a first die and a receiving device disposed on a second die. During the transmission process in which the transmitting device transmits a data unit stream to the receiving device through a native lane, after the native lane is determined to be a degraded lane, the transmitting device transmits a synchronization flag to the receiving device through a redundant lane to notify a repair time point. During the uninterrupted transmission process of the data unit stream, the transmitting device uses the redundant lane instead of the degraded lane based on the repair time point, and the receiving device uses the redundant lane instead of the degraded lane based on the repair time point notified by the synchronization flag.Type: ApplicationFiled: July 6, 2023Publication date: January 9, 2025Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Igor Elkanovich, Yung-Sheng Fang, Pei Yu
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Publication number: 20240394210Abstract: A die-to-die communication system and an operation method thereof are provided. The die-to-die communication system includes a transmitting device disposed at a first die and a receiving device disposed at a second die, wherein the first die and second die are disposed in a same integrated circuit package. The receiving device is coupled to the transmitting device via a communication interface. The transmitting device transmits a data unit stream to a data channel in the communication interface. The receiving device receives the data unit stream from the data channel in the communication interface. The receiving device returns transmission management information to the transmitting device via a feedback channel different from the data channel in the communication interface. In various embodiments, the transmission management information includes flow control information and/or error replay information.Type: ApplicationFiled: May 23, 2023Publication date: November 28, 2024Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Sheng Fang, Igor Elkanovich, Pei Yu
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Patent number: 12126350Abstract: A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.Type: GrantFiled: November 21, 2022Date of Patent: October 22, 2024Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Hao Wang, Hui-Wen Tsai, Shih-Chun Lo
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Publication number: 20240344901Abstract: A temperature sensing device and a calibration method of the temperature sensing device are provided. Based on different conditions, the temperature sensing device generates a first digital sensing value and a second digital sensing value corresponding to an ambient temperature. The temperature sensing device generates a first sensing result value according to the first digital sensing value, a first compensation value, and a sensing difference value between the first digital sensing value and the second digital sensing value, and generates a second sensing result value according to the second digital sensing value, a second compensation value, and the sensing difference value. The temperature sensing device obtains an error from the first sensing result value and the second sensing result value according to a first reference value and a second reference value. The temperature sensing device calibrates the first compensation value according to the error.Type: ApplicationFiled: June 7, 2023Publication date: October 17, 2024Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Hao Wang, Jun-Wan Wu, Pei-Ju Lin
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Patent number: 12117864Abstract: An interface device and a signal transceiving method thereof are provided. The interface device includes a master circuit and a slave circuit. The slave circuit includes a second receiver, a clock generator, a sampler, and a comparator. The first receiver and second receiver respectively receive input data and a clock signal from the master circuit. The clock generator delays the clock signal according to a delay value to generate a delayed clock signal, and generates a plurality of sampling signals according to the delayed clock signal. The sampler samples the input data according to the sampling signals to generate a plurality of sampling results. The comparator compares the sampling results to generate a comparison result. The clock generator adjusts the delay value according to the comparison result.Type: GrantFiled: September 23, 2022Date of Patent: October 15, 2024Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bi-Yang Li, Igor Elkanovich, Hung-Yi Chang, Shih-Cheng Kao
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Publication number: 20240322413Abstract: A high-frequency transmission element is provided. The high-frequency transmission element includes a connecting wire structure and an impedance matching plate structure. The connecting wire structure includes a connecting wire and a connecting pad. The connecting pad is located at an end of the connecting wire. The impedance matching plate structure includes an impedance matching plate body, an opening, and an impedance matching portion. The connecting pad is located in a projection range of the opening in a direction of orthographic projection of the impedance matching plate structure. The impedance matching portion is located in a periphery of the opening and extends in the direction from the connecting wire towards the connecting pad.Type: ApplicationFiled: April 10, 2023Publication date: September 26, 2024Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Yi Liao, Yu-Lin Cheng, Chi-Lou Yeh, Sheng-Fan Yang
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Patent number: 12093202Abstract: The disclosure provides a data bus inversion (DBI) encoding device and a DBI encoding method. The DBI encoding device includes a comparator circuit, a first controllable inverting circuit and a second controllable inverting circuit. The comparator circuit checks the number of the different bits between a first raw data and a second raw data. Based on the number of the different bits, the first controllable inversion circuit determines whether to invert a first DBI bit corresponding to the first raw data as a second DBI bit corresponding to the second raw data. The second controllable inversion circuit determines, based on the second DBI bit, whether to adopt the second raw data as a second encoded data corresponding to the second raw data, or invert the second raw data to generate the second encoded data.Type: GrantFiled: December 12, 2022Date of Patent: September 17, 2024Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Sheng Fang, Igor Elkanovich, Pei Yu
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Patent number: 12066968Abstract: A communication interface structure and a Die-to-Die package are provided. The communication interface structure includes first bumps arranged in a first row-column configuration, second bumps arranged in a second row-column configuration, and conductive lines disposed between the first bumps and the second bumps to connect each of the first bumps to each of the second bumps. The first bumps in neighboring rows are alternately shifted with each other. The second bumps are disposed under or over the first bumps, wherein each of the second bumps in even rows is at a position shifted in a column direction from a center of each of the first bumps in the even rows, and each of the second bumps in odd rows is at a position between two of the second bumps in the even rows in the column direction.Type: GrantFiled: July 13, 2022Date of Patent: August 20, 2024Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Fan Yang, Chih-Chiang Hung, Yuan-Hung Lin, Shih-Hsuan Hsu, Igor Elkanovich
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Publication number: 20240210252Abstract: A temperature sensing device and a temperature sensing method are provided. The temperature sensing device includes a sensor and a conversion circuit. The sensor generates a first sensing signal and a second sensing signal corresponding to a temperature based on different conditions. The conversion circuit performs a subtraction operation on the first sensing signal and the second sensing signal to obtain a result difference value, calculates a compensation value according to the result difference value and the first sensing signal, multiplies the result difference value and the compensation value to obtain a multiplication value, subtracts the multiplication value from the first sensing signal to generate a first value, adds the multiplication value to the first sensing signal to generate a second value, and divides the first value by the second value to generate an output value. The second value is a constant.Type: ApplicationFiled: January 11, 2023Publication date: June 27, 2024Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Hao Wang, Jun-Wan Wu, Pei-Ju Lin
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Publication number: 20240193114Abstract: The disclosure provides a data bus inversion (DBI) encoding device and a DBI encoding method. The DBI encoding device includes a comparator circuit, a first controllable inverting circuit and a second controllable inverting circuit. The comparator circuit checks the number of the different bits between a first raw data and a second raw data. Based on the number of the different bits, the first controllable inversion circuit determines whether to invert a first DBI bit corresponding to the first raw data as a second DBI bit corresponding to the second raw data. The second controllable inversion circuit determines, based on the second DBI bit, whether to adopt the second raw data as a second encoded data corresponding to the second raw data, or invert the second raw data to generate the second encoded data.Type: ApplicationFiled: December 12, 2022Publication date: June 13, 2024Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Sheng Fang, Igor Elkanovich, Pei Yu
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Publication number: 20240152418Abstract: A communication system and an operation method thereof are provided. A transmitting device transmits a data unit to a receiving device through a data channel of a communication interface. The transmitting device calculates an original verification information unit of the data unit and synchronously transmits the original verification information unit to the receiving device through a verification information channel of the communication interface based on a transmission timing of the data unit in the data channel. After receiving a current data unit and before receiving a next data unit, the receiving device verifies whether the current data unit received from the data channel has errors in real time based on a current original verification information unit corresponding to the current data unit.Type: ApplicationFiled: November 8, 2022Publication date: May 9, 2024Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Igor Elkanovich, Yung-Sheng Fang, Pei Yu, Chang-Ming Liu
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Publication number: 20240072772Abstract: An interface device and a signal transceiving method thereof are provided. The interface device includes a slave circuit and a master circuit. The slave circuit is coupled to the master circuit and includes a first programmable delay line, a first output clock generator, and a first phase detector. The first programmable delay line provides a first adjusting delay amount according to a first adjust signal, and generates a first delayed clock signal by delaying a first clock signal according to the first adjusting delay amount. The first output clock generator generates a second clock signal according to the first delayed clock signal. The first phase detector detects a phase difference of the first clock signal and the second clock signal to generate first phase lead or lag information. The first adjust signal is generated according to the first phase lead or lag information.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bi-Yang Li, Igor Elkanovich, Hung-Yi Chang, Shih-Cheng Kao
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Publication number: 20240072816Abstract: A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.Type: ApplicationFiled: November 21, 2022Publication date: February 29, 2024Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Hao Wang, Hui-Wen Tsai, Shih-Chun Lo
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Patent number: 11902171Abstract: A communication system and an operation method thereof are provided. The transmitting device transmits the current data unit and the transmitted data verification information to the receiving device through the communication interface, and records the current data unit in an FIFO buffer. The receiving device counts the received data identification value by itself based on the current data unit received from the communication interface. The receiving device uses the received data identification value and the transmitted data verification information to check whether the current data unit received from the communication interface has errors. When the current data unit is in error, the receiving device returns an error flag to the transmitting device so that the transmitting device suspends the transmission of the new data unit, and transmits the buffered data unit recorded in the FIFO buffer to the receiving device through the communication interface.Type: GrantFiled: July 30, 2021Date of Patent: February 13, 2024Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chang-Ming Liu, Yung-Sheng Fang, Pei Yu, Igor Elkanovich, Chia-Chien Tu
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Publication number: 20240020260Abstract: A communication interface structure and a Die-to-Die package are provided. The communication interface structure includes first bumps arranged in a first row-column configuration, second bumps arranged in a second row-column configuration, and conductive lines disposed between the first bumps and the second bumps to connect each of the first bumps to each of the second bumps. The first bumps in neighboring rows are alternately shifted with each other. The second bumps are disposed under or over the first bumps, wherein each of the second bumps in even rows is at a position shifted in a column direction from a center of each of the first bumps in the even rows, and each of the second bumps in odd rows is at a position between two of the second bumps in the even rows in the column direction.Type: ApplicationFiled: July 13, 2022Publication date: January 18, 2024Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Fan Yang, Chih-Chiang Hung, Yuan-Hung Lin, Shih-Hsuan Hsu, Igor Elkanovich
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Publication number: 20240014174Abstract: An interface for a semiconductor chip provided herein includes bonds. The interface has device layout channels and via layout channels and including a circuitry and routing structure. Each device layout channel is located between two via layout channels in a first direction to form a unit layout channel extending in a second direction intersecting the first direction. The bonds are arranged in a bond map following the via layout channels and outside the device layout channels. Most adjacent two of the bonds in the second direction are arranged in a vertical pitch, two bonds at two opposite sides of the device layout channel in the first direction are arranged in a transversal pitch, and the transversal pitch is greater than the vertical pitch. A portion of the circuitry and routing structure is disposed in the device layout channels. A semiconductor device including stacked semiconductor chips is also provided.Type: ApplicationFiled: July 5, 2022Publication date: January 11, 2024Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chih Chen, Kun-Ti Lee, Chih-Kang Chiu, Igor Elkanovich
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Publication number: 20240012442Abstract: An interface device and a signal transceiving method thereof are provided. The interface device includes a master circuit and a slave circuit. The slave circuit includes a second receiver, a clock generator, a sampler, and a comparator. The first receiver and second receiver respectively receive input data and a clock signal from the master circuit. The clock generator delays the clock signal according to a delay value to generate a delayed clock signal, and generates a plurality of sampling signals according to the delayed clock signal. The sampler samples the input data according to the sampling signals to generate a plurality of sampling results. The comparator compares the sampling results to generate a comparison result. The clock generator adjusts the delay value according to the comparison result.Type: ApplicationFiled: September 23, 2022Publication date: January 11, 2024Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bi-Yang Li, Igor Elkanovich, Hung-Yi Chang, Shih-Cheng Kao