Abstract: A die-to-die communication system and an operation method thereof are provided. The die-to-die communication system includes a transmitting device disposed at a first die and a receiving device disposed at a second die, wherein the first die and second die are disposed in a same integrated circuit package. The receiving device is coupled to the transmitting device via a communication interface. The transmitting device transmits a data unit stream to a data channel in the communication interface. The receiving device receives the data unit stream from the data channel in the communication interface. The receiving device returns transmission management information to the transmitting device via a feedback channel different from the data channel in the communication interface. In various embodiments, the transmission management information includes flow control information and/or error replay information.

Abstract: An interface device and a signal transceiving method thereof are provided. The interface device includes a slave circuit and a master circuit. The slave circuit is coupled to the master circuit and includes a first programmable delay line, a first output clock generator, and a first phase detector. The first programmable delay line provides a first adjusting delay amount according to a first adjust signal, and generates a first delayed clock signal by delaying a first clock signal according to the first adjusting delay amount. The first output clock generator generates a second clock signal according to the first delayed clock signal. The first phase detector detects a phase difference of the first clock signal and the second clock signal to generate first phase lead or lag information. The first adjust signal is generated according to the first phase lead or lag information.

Abstract: A probe card device includes a wiring board provided with a plurality of contacts, a probe head having a probe holder and a plurality of conductive probes arranged on the probe holder, respectively, and a circuit protection assembly including an insulation plate, a plurality of through holes and a plurality of self-resetting fusing elements. The insulation plate is sandwiched between the wiring board and the probe head. The through holes are respectively formed on the insulation plate and arranged in an array form. The self-resetting fusing elements are respectively disposed within the through holes. Each of the self-resetting fusing elements is electrically connected to one of the contacts and one of the conductive probes for reversibly breaking down electric currents from the wiring board to the conductive probe.

Abstract: A communication system and an operation method thereof are provided. A transmitting device transmits a data unit to a receiving device through a data channel of a communication interface. The transmitting device calculates an original verification information unit of the data unit and synchronously transmits the original verification information unit to the receiving device through a verification information channel of the communication interface based on a transmission timing of the data unit in the data channel. After receiving a current data unit and before receiving a next data unit, the receiving device verifies whether the current data unit received from the data channel has errors in real time based on a current original verification information unit corresponding to the current data unit.

Abstract: A semiconductor chiplet device includes a package substrate, an interposer layer, a first die and a second die. The first die includes a first interface, and the second die includes a second interface. A first side of the interposer layer is configured to arrange the first die and the second die. The first die and the second die perform a data transmission through the first interface, the interposer layer and the second interface. The package substrate is arranged on a second side of the interposer layer, and includes a decoupling capacitor. The decoupling capacitor is arranged between the first interface and the second interface, or arranged in a vertical projection area of the first interface and the second interface on the package substrate.

Abstract: A semiconductor chip includes a physical layer and a processing circuit. The physical layer includes at least one sequence checking circuit and at least one signal transmission path, wherein the at least one sequence checking circuit is configured to generate at least one test result signal according to a clock signal and at least one test data signal transmitted through the at least one signal transmission path, and the clock signal is not transmitted through the at least one signal transmission path. The processing circuit is electrically coupled to the physical layer and is configured to determine an operation status of the at least one signal transmission path according to the voltage level of the at least one test result signal.

Abstract: The disclosure provides a communication system between dies and a repairing method for lanes between dies. The communication system includes a transmitting device disposed on a first die and a receiving device disposed on a second die. During the transmission process in which the transmitting device transmits a data unit stream to the receiving device through a native lane, after the native lane is determined to be a degraded lane, the transmitting device transmits a synchronization flag to the receiving device through a redundant lane to notify a repair time point. During the uninterrupted transmission process of the data unit stream, the transmitting device uses the redundant lane instead of the degraded lane based on the repair time point, and the receiving device uses the redundant lane instead of the degraded lane based on the repair time point notified by the synchronization flag.

Abstract: A die-to-die communication system and an operation method thereof are provided. The die-to-die communication system includes a transmitting device disposed at a first die and a receiving device disposed at a second die, wherein the first die and second die are disposed in a same integrated circuit package. The receiving device is coupled to the transmitting device via a communication interface. The transmitting device transmits a data unit stream to a data channel in the communication interface. The receiving device receives the data unit stream from the data channel in the communication interface. The receiving device returns transmission management information to the transmitting device via a feedback channel different from the data channel in the communication interface. In various embodiments, the transmission management information includes flow control information and/or error replay information.

Abstract: A testing apparatus includes a circuit board, a probe station and a probe array. The circuit board includes a plurality of contacts. The probe station includes a platform located on the circuit board and used for carrying a device under test (DUT), and a plurality of probe holes formed on the platform and arranged in an array. The probe array includes a plurality of telescopic probes respectively linearly inserted into the probe holes. One end of each of the telescopic probes is contacted with one of the contacts, and the other end thereof is contacted with one of solder balls of the DUT. Each of the probe holes includes an elongated groove penetrating through the platform. Each of the telescopic probes is provided with a fin protruding outwardly and inserting into the elongated groove.

Abstract: A calibration system includes a jitter-capturing analog-to-digital converter (ADC), a calibration value generating circuit and a first calculation circuit. The jitter-capturing ADC is configured to sample a to-be-sampled clock signal according to an operating clock signal to generate a first quantized output. The calibration value generating circuit is configured to receive the first quantized output and a second quantized output of a to-be-calibrated ADC to generate a calibration value. The operating clock signal is for driving the to-be-calibrated ADC to sample, and the calibration value is related to a phase noise of the operating clock signal. The first calculation circuit is coupled with the calibration value generating circuit, and configured to subtract the calibration value from the second quantized output to generate a third quantized output.

Abstract: A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.

Abstract: A temperature sensing device and a calibration method of the temperature sensing device are provided. Based on different conditions, the temperature sensing device generates a first digital sensing value and a second digital sensing value corresponding to an ambient temperature. The temperature sensing device generates a first sensing result value according to the first digital sensing value, a first compensation value, and a sensing difference value between the first digital sensing value and the second digital sensing value, and generates a second sensing result value according to the second digital sensing value, a second compensation value, and the sensing difference value. The temperature sensing device obtains an error from the first sensing result value and the second sensing result value according to a first reference value and a second reference value. The temperature sensing device calibrates the first compensation value according to the error.

Abstract: An interface device and a signal transceiving method thereof are provided. The interface device includes a master circuit and a slave circuit. The slave circuit includes a second receiver, a clock generator, a sampler, and a comparator. The first receiver and second receiver respectively receive input data and a clock signal from the master circuit. The clock generator delays the clock signal according to a delay value to generate a delayed clock signal, and generates a plurality of sampling signals according to the delayed clock signal. The sampler samples the input data according to the sampling signals to generate a plurality of sampling results. The comparator compares the sampling results to generate a comparison result. The clock generator adjusts the delay value according to the comparison result.

Abstract: A high-frequency transmission element is provided. The high-frequency transmission element includes a connecting wire structure and an impedance matching plate structure. The connecting wire structure includes a connecting wire and a connecting pad. The connecting pad is located at an end of the connecting wire. The impedance matching plate structure includes an impedance matching plate body, an opening, and an impedance matching portion. The connecting pad is located in a projection range of the opening in a direction of orthographic projection of the impedance matching plate structure. The impedance matching portion is located in a periphery of the opening and extends in the direction from the connecting wire towards the connecting pad.

Abstract: The disclosure provides a data bus inversion (DBI) encoding device and a DBI encoding method. The DBI encoding device includes a comparator circuit, a first controllable inverting circuit and a second controllable inverting circuit. The comparator circuit checks the number of the different bits between a first raw data and a second raw data. Based on the number of the different bits, the first controllable inversion circuit determines whether to invert a first DBI bit corresponding to the first raw data as a second DBI bit corresponding to the second raw data. The second controllable inversion circuit determines, based on the second DBI bit, whether to adopt the second raw data as a second encoded data corresponding to the second raw data, or invert the second raw data to generate the second encoded data.

Abstract: A communication interface structure and a Die-to-Die package are provided. The communication interface structure includes first bumps arranged in a first row-column configuration, second bumps arranged in a second row-column configuration, and conductive lines disposed between the first bumps and the second bumps to connect each of the first bumps to each of the second bumps. The first bumps in neighboring rows are alternately shifted with each other. The second bumps are disposed under or over the first bumps, wherein each of the second bumps in even rows is at a position shifted in a column direction from a center of each of the first bumps in the even rows, and each of the second bumps in odd rows is at a position between two of the second bumps in the even rows in the column direction.

Abstract: A temperature sensing device and a temperature sensing method are provided. The temperature sensing device includes a sensor and a conversion circuit. The sensor generates a first sensing signal and a second sensing signal corresponding to a temperature based on different conditions. The conversion circuit performs a subtraction operation on the first sensing signal and the second sensing signal to obtain a result difference value, calculates a compensation value according to the result difference value and the first sensing signal, multiplies the result difference value and the compensation value to obtain a multiplication value, subtracts the multiplication value from the first sensing signal to generate a first value, adds the multiplication value to the first sensing signal to generate a second value, and divides the first value by the second value to generate an output value. The second value is a constant.

Abstract: The disclosure provides a data bus inversion (DBI) encoding device and a DBI encoding method. The DBI encoding device includes a comparator circuit, a first controllable inverting circuit and a second controllable inverting circuit. The comparator circuit checks the number of the different bits between a first raw data and a second raw data. Based on the number of the different bits, the first controllable inversion circuit determines whether to invert a first DBI bit corresponding to the first raw data as a second DBI bit corresponding to the second raw data. The second controllable inversion circuit determines, based on the second DBI bit, whether to adopt the second raw data as a second encoded data corresponding to the second raw data, or invert the second raw data to generate the second encoded data.

Abstract: A communication system and an operation method thereof are provided. A transmitting device transmits a data unit to a receiving device through a data channel of a communication interface. The transmitting device calculates an original verification information unit of the data unit and synchronously transmits the original verification information unit to the receiving device through a verification information channel of the communication interface based on a transmission timing of the data unit in the data channel. After receiving a current data unit and before receiving a next data unit, the receiving device verifies whether the current data unit received from the data channel has errors in real time based on a current original verification information unit corresponding to the current data unit.

Abstract: An analog-to-digital converting device includes N-stage first analog-to-digital converters (ADCs), a second ADC, a first calibration circuit, a data recovery circuit and an output circuit. The N-stage first ADCs has a first sampling frequency that is (N+1)/N times of a second sampling frequency, and converts an input signal into first quantized outputs. The second ADC has the second sampling frequency, and converts the input signal into a second quantized output. The first calibration circuit calibrates offsets of the first quantized outputs and the second quantized output to generate third quantized outputs and a fourth quantized output. The data recovery circuit outputs, by the second sampling frequency, one of the third quantized outputs as a fifth quantized output, and subtracts the fifth quantized output from the fourth quantized output to generate output data. The output circuit generates an output signal according to the third quantized outputs and the output data.