Abstract: Phase offset cancellation circuit and associated clock generator, include a first modifying phase interpolator and a second modifying phase interpolator, and provide a first modified clock and a second modified clock according to a first to a fourth input clocks; wherein the first and the third clocks are of opposite phases. The first modifying phase interpolator performs equal phase interpolation between the first and the second input clocks to generate the first modified clock, and the second modifying phase interpolator performs equal phase interpolation between the third and the fourth input clocks to generate the second modified clock, such that a phase difference between the first modified clock and the second modified clock is of substantially 90 degrees, against phase offsets between the first to the fourth input clocks.

Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.

Abstract: A current-mode D latch includes a first load element, a second load element, a first bias current source, a first switch transistor, a second switch transistor, a first stage circuit and a second stage circuit. The first switch transistor is controlled by an inverted reset signal. The second switch transistor is controlled by a reset signal. When an inverted clock signal is in a first level state and the reset signal is inactive, the first input signal is converted into the first output signal and the first inverted input signal is converted into the first inverted output signal by the first stage circuit. When a clock signal is in the first level state and the reset signal is inactive, the first output signal and the first inverted output signal are maintained by the second stage circuit.

Abstract: Eye diagram scan circuit and associated method for a receiver circuit, including a level adjust circuit, a phase interpolator and a control module. The receiver circuit provides a first data signal and a primary phase data according to a received signal. The control module provides a phase offset data and a level offset data. The level adjust circuit adjusts a level of the received signal in respond to the level offset data; the phase interpolator triggers according to a sum of the phase offset data and the primary phase data, so a second data signal is provide in response to the level-adjusted received signal. The control module compares the first data signal and the second data signal, and accordingly provides an eye diagram scan result for the phase offset data and the level offset data.

Abstract: A receiver circuit receives an incoming signal and accordingly provides an internal signal, and includes an equalizer, a slicer module and a counter module. The equalizer provides a signal level according to the incoming signal, the slicer module compares if the internal signal exceeds a level range; according to comparison result, the counter module provides a signal quality indication capable of indicating whether a bit error rate of signal receiving is greater than a predetermined reference bit error rate. One of an upper bound and a lower bound of the level range can equal the signal level, a distance between the upper bound and the lower bound is set according to a reference signal-to-noise ratio which associates with the reference bit error rate.

Abstract: Electronic test system and associated method, including a first and a second connection terminals respectively coupled to two pins of a chip under test, a signal source terminal coupled to a signal generator, a first and a second measurement terminals coupled to a tester, a fifth switch, a seventh switch and a switch circuit which has a first and a fourth front terminals coupled to the signal source terminal, has a first and a fourth back terminals coupled to the first and second connection terminals, and controls conduction between the first front terminal and the first back terminal, as well as conduction between the fourth front terminal and the fourth back terminal. The fifth switch is coupled between the fourth back terminal and the first measurement terminal, and the seventh switch is coupled between the first connection terminal and the second measurement terminal.

Abstract: A DC converter is provided for converting a first supply voltage into a second supply voltage. The first supply voltage is higher than the second supply voltage. The DC converter includes a driving stage and an output stage. The driving stage includes a modulation circuit, a pull-up driving unit, a pull-up unit, a pull-down driving unit, and a pull-down unit. The modulation circuit generates a control signal according to the second supply voltage. The pull-up driving unit generates a first P-type driving signal and a second P-type driving signal to the pull-up unit according to the control signal. The pull-down driving unit generates a first N-type driving signal and a second N-type driving signal to the pull-down unit according to the control signal.

Abstract: A hybrid electronic design system and a reconfigurable connection matrix thereof are disclosed. The electronic design system includes a virtual unit, a hybrid unit and a communication channel. The virtual unit further includes a plurality of proxy units, a plurality of virtual components and a driver. The virtual components are connected with the driver via the proxy units. The hybrid unit further includes an emulate unit, a physical unit and a chip level transactor. The chip level transactor is connected with the emulate unit and the physical unit. The communication channel is connected with the driver of the virtual unit and the chip level transactor of the hybrid unit.

Abstract: ESD protection circuit is provided, which includes a detection circuit, a trigger circuit and a clamp circuit. The detection circuit includes two stacked capacitors reflecting occurrence of ESD events. The trigger circuit includes three stacked transistors controlling triggering of the clamp circuit according to operation of the detection circuit. The clamp circuit includes two stacked transistors conducting ESD path when triggered.

Abstract: A high speed level shifter is provided for converting a low input voltage into a wide-range high output voltage. By utilizing two switching units to improve the latching speed of the latching unit of the level shifter, the duty cycle of the input signal is nearly equal to the duty cycle of the output signal.

Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.

Abstract: The invention discloses a power gating for in-rush current mitigation. Firstly the circuit uses small power switch cells at first stage, such that those power switch cells run in saturation region. Secondly a delay unit delays a switch signal to control the dwell time of current to reduce the peak value of the current. Thirdly large power switch cells are used at the rest, such that those power switch cells operate in linear region.

Abstract: This invention provides a clock and data recovery system, which comprises a plurality of gm cells, control device, resistor and capacitor. The gm cells respectively have an input end and an output end. The control devices are connected to these output ends. According to a time value, the control device controls a part of the plurality of gm cells to form a first gm cell, and the control device controls another part of the plurality of gm cells to form a second gm cell. The resistor is connected between the first gm cell and the second gm cell. The capacitor is connected to the second gm cell. Wherein, the control device controls the ratio of the first gm cell and the second gm cell in accordance with a time-division multiplexed manner.

Abstract: A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.

Abstract: The invention creates a slicing level and sampling phase adaptation circuitry for data recovery systems. The invention explores the boundary of the eye opening to decide the optimal slicing level and sampling phase with a simple bit error rate estimation technique. Bit error rate estimation is achieved with several collaborating samplers.

Abstract: A burn-in socket for carrying an electronic device to let the electronic device electrically connect to a circuit board via the burn-in socket is provided. The electronic device has a body and at least a lead. The burn-in socket comprises a frame and a carrier, the frame has an opening and a plurality of first aligning potions, wherein the opening fits onto the contour of the body, and the first aligning portions surrounds the opening. The carrier has a plurality of second aligning portions. The frame is assembled to the carrier with the conjunction of the first aligning portions and the second aligning portions. The body is capable of fitting into the opening to let the lead electrically connect to the circuit board via the carrier.

Abstract: A through-silicon via (TSV) testing structure is disclosed herein and includes a plurality of controllers, a plurality of transmitters and a plurality of receivers. The controllers are configured to output a first controlling signal and a second controlling signal. The transmitters are respectively connected to the output end of the through-silicon via and one of the controllers, and output a testing output signal in accordance with the first controlling signal and the second controlling signal. The receivers are respectively connected to the input end of the through-silicon via and another one of the controllers, and input a testing input signal in accordance with the first controlling signal and the second controlling signal.

Abstract: A boundary scan circuit containing a freeze circuit and a transparency circuit that provides a capability to selectively place portions of a system logic in a sleep mode and thereby conserving power. There are two transparency circuit configurations, one that connects to an input pad cell and one that connects to an output pad cell. The circuitry in the transparency circuit is controlled in such a manner as to establish at the output of transparency circuit a known logic state to control leakage current resulting from the circuitry of the various pad cell configurations, which further conserves power during sleep mode.

Abstract: The invention discloses a data transfer protection apparatus for a flash memory controller, placed between Bose-Chaudhuri-Hocquenghem (BCH) and NAND Flash Chip. In encode path the hardware module selects a sequence of constant values, exclusive-or the original parity with that constant value. In decode path the hardware module detects the parity period, exclusive-or the parity which is read out from NAND Flash Chip with the same constant value sequence.

Abstract: A device for storing pulse latch with logic circuit and thus having signal maintaining function is provided, wherein the device is composed of a data signal, a scan data input signal, a stored signal, a choosing data input signal, a time clock signal, a restoring signal, a first signal channel, a scan latch, a second signal channel, a pulse latch, a normal output signal, an output signal, a first OR gate, a second OR gate, a third OR gate, a AND gate and an inverter connecting to one another. The device may store the data when being switch off and restore the data when being switch on again.