Abstract: A temperature sensing device and a temperature sensing method are provided. The temperature sensing device includes a sensor and an analog-to-digital converter. The sensor generates a first sensing result corresponding to an ambient temperature based on a first condition and generates a second sensing result corresponding to the ambient temperature based on a second condition. The second sensing result is different from the first sensing result. The analog-to-digital divides the first sensing result and the second sensing result to obtain a quotient value and generates an output digital code value corresponding to the ambient temperature according to the quotient value.

Abstract: A routing structure between dies is provided, including a trace layer, disposed on a substrate, wherein a plurality of routing paths is embedded in the trace layer. In addition, a first die and a second die are disposed on the trace layer and connected by the routing paths. A spacing gap between the first die and the second die is along a first direction and interfacing edges of the first die and the second die are extending along a second direction perpendicular to the first direction. Each of the routing paths includes a first straight portion in parallel to connect to the interfacing edges. The first straight portion has a slant angle with respect to the first direction other than 0° and 90°.

Abstract: A communication interface structure for connection between dies is provided, including a memory die, processing dies and interconnection routings. The memory die includes a first interface edge, wherein the first interface edge is split into a plurality of interface groups. Each of the processing dies includes a second interface edge. Interconnection routings respectively connect the second interface edges of the processing dies to the interface groups of the memory die.

Abstract: An electronic system, an integrated circuit die and an operation method thereof are provided. The integrated circuit die includes a plurality of interface circuit slices and a merging circuit. The transmission data stream sent from the transmitter die is split into a plurality of sub-data streams. Each of the interface circuit slices provides a physical layer to receive the corresponding one of the sub-data streams. The merging circuit is coupled to the interface circuit slices to receive the sub-data streams. The merging circuit merges the sub-data streams from the interface circuit slices back to the original data corresponding to the transmission data stream to be provided to an application layer. The merging circuit aligns the sub-data streams from the interface circuit slices in timing to mitigate different delays of the interface circuit slices.

Abstract: A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.

Abstract: An interface of integrated circuit (IC) die includes a plurality of the contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmitting group and a receiving group. The contact elements of the transmitting group have a first contact element sequence and the contact elements of the receiving group have a second contact element sequence, the first contact element sequence is identical to the second contact element sequence. The contact elements with the first contact element sequence and the second contact element sequence are matched when the contact element pattern is geometrically rotated by 180° with respect to a row direction and a column direction.

Abstract: A circuit of communication interface between dies is provided. The circuit includes a first interface of the first die having a serializer to serialize an input data of N bits a serialized data for transmitting out and a second interface of the second die having a de-serializer to receive and deserialize the serialized data into a de-serialized data. In addition, an interconnection structure connected between the first die and the second die to connect the serializer and the de-serializer, wherein the interconnection structure is an interposer or a redistribution layer of a semiconductor structure to form a parallel bus for transmitting the serialized data in one line of the parallel bus between the first die and the second die. A clock generator provides a first clock to a first ripple counter of the serializer and a second clock to a second ripple counter of the de-serializer.

Abstract: A testing apparatus including a base and a preheating unit arranged on the base is provided. The preheating unit includes a gas generator, a blocking mechanism and a heating device. The gas generator is configured to discharge air toward the base to form an air wall. The blocking mechanism is located above the air wall and forms a heat preservation space with the air wall. The heating device is arranged in the heat preservation space.

Abstract: An inspecting device including a carrier, multiple telescopic probes, a locking component and a conductive structure is provided. The carrier has a through hole and a ground pad corresponding to the through hole. The through hole penetrates from the first surface to the second surface of the carrier, and the ground pad is disposed on the second surface. The telescopic probes are disposed in parallel on the first surface of the carrier. The locking component passes through the through hole and is disposed between two adjacent telescopic probes of the multiple telescopic probes. The locking component includes a screw. A head of the screw has a first pitch and a second pitch, and a density of the first pitch is different from a density of the second pitch. The conductive structure is partially embedded in the locking component, and the conductive structure, the locking component and the ground pad are electrically connected.

Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.

Abstract: A temperature sensing device and a temperature sensing method are provided. The temperature sensing device includes a sensor and an analog-to-digital converter. The sensor generates a first sensing result corresponding to an ambient temperature based on a first condition and generates a second sensing result corresponding to the ambient temperature based on a second condition. The second sensing result is different from the first sensing result. The analog-to-digital divides the first sensing result and the second sensing result to obtain a quotient value and generates an output digital code value corresponding to the ambient temperature according to the quotient value.

Abstract: A fixing device and a fixing method for a clock tree are provided. The fixing method for the clock tree includes: performing a clock signal path tracking operation on a netlist of a circuit according to timing constraint information to obtain a clock tree circuitry structure; identifying a convergency status of the clock tree circuitry structure to find out at least one clock convergence point, and setting one of a plurality of clock signals on the clock convergence point as a selected clock signal; performing a fix point identification operation on the clock tree circuitry structure based on the selected clock signal to obtain a plurality of candidate fix points; and calculating a plurality weighting values of the candidate fix points, obtaining a plurality of selected fixed points according to the weighting values.

Abstract: An apparatus for adjusting skew of circuit signal and an adjusting method thereof are provided. The adjusting method includes: providing a controller for executing: based on each of a plurality of clock signals, dividing a circuit to generate a plurality of circuit partitions according to a netlist of the circuit; grouping the circuit partitions to respectively generate a plurality of circuit groups; identifying adjacent states of layout areas of the circuit groups; and, adjusting a skew value of each of the circuit groups according to the adjacent states.

Abstract: A probe card module including a probe card assembly and a strengthening structure is provided. The probe card assembly includes a first surface, a second surface opposite to the first surface, and a plurality of probes protruding from the first surface. The second surface includes a central zone and a peripheral zone surrounding the central zone. Projections of the probes on the second surface are located at the central zone. The strengthening structure is disposed on the second surface and includes two support bases which protrude from the peripheral zone and are away from each other, and the strengthening structure also includes an arc-shaped reinforcement assembly connected to the two support bases, where the arc-shaped reinforcement assembly protrudes toward and leans against the central zone.

Abstract: An interface for a semiconductor device includes a master device and a plurality of slave devices. The interface includes a master interface and a slave interface. The master interface is implemented in the master device and includes a master bond pattern of master bonds arranged as a first array. The slave interface is implemented each slave device and includes a slave bond pattern of slave bonds arranged as a second array. The first array of the master bonds includes a first central row and first data rows in two parts being symmetric to the first central row. The second array of the slave bonds includes a second central row and second data rows in two parts being symmetric to the second central row. The first central row and the second central row are aligned in connection, and the first data rows are connected to the second data rows.

Abstract: An establishing method for the timing model includes: identifying at least one first victim path which is a boundary path in a circuit block; determining whether to remove a first aggressor path corresponding to the first victim path according to a transmission delay on the first victim path; finding a plurality of high-fanout circuit devices with a fanout number greater than a preset value in the circuit block; determining whether to remove each of the high-fanout circuit devices according to a connection position of each of the high-fanout circuit devices; identifying a plurality of second victim paths corresponding to each of the high-fanout circuit devices, and determining whether to keep or remove a second aggressor path corresponding to each of the second victim paths according to a transmission delay of each of the second victim paths.

Abstract: A probe card module including a probe card assembly and a strengthening structure is provided. The probe card assembly includes a first surface, a second surface opposite to the first surface, and a plurality of probes protruding from the first surface. The second surface includes a central zone and a peripheral zone surrounding the central zone. Projections of the probes on the second surface are located at the central zone. The strengthening structure is disposed on the second surface and includes two support bases which protrude from the peripheral zone and are away from each other, and the strengthening structure also includes an arc-shaped reinforcement assembly connected to the two support bases, where the arc-shaped reinforcement assembly protrudes toward and leans against the central zone.

Abstract: A frame decoding circuit implemented in an IC die includes a frame synchronizer, receiving an input clock signal and an input frame signal in serial form, to provide an output clock signal. A phase shift of the output clock signal is adjusted according to a detected code by sampling the input frame signal at a center point for every two bits and the detected code being not a correct type. The input clock signal is divided in frequency with the phase shift for providing the output clock signal. A de-serializer unit receives the input frame signal, the input data, the output clock signal from the frame synchronizer, a delay-locked-loop clock signal to de-serialize the input frame signal and the input data for output.