Abstract: The invention discloses to a method to synchronize and synthesize bus transaction traces for an un-timed virtual environment. The steps are the followings providing a simulation environment and an emulation environment; recording the transaction of intellectual property (IP) through the bus, collecting the plurality of continuously transferred transaction set, connecting a plurality of transaction blocks recorded from the simulation environment, and assigning a corresponding number to the transaction block; labeling a begin time mark and a transfer time mark; initializing a plurality of parameters; taking a transaction block; judging the type of the transaction block respectively; and after respectively assuring that the transaction block is the last transaction block in the simulated transaction block series, output these parameter values.

Abstract: A hybrid electronic design system and a reconfigurable connection matrix thereof are disclosed. The electronic design system includes a virtual unit, a hybrid unit and a communication channel. The virtual unit further includes a plurality of proxy units, a plurality of virtual components and a driver. The virtual components are connected with the driver via the proxy units. The hybrid unit further includes an emulate unit, a physical unit and a chip level transactor. The chip level transactor is connected with the emulate unit and the physical unit. The communication channel is connected with the driver of the virtual unit and the chip level transactor of the hybrid unit.

Abstract: The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Abstract: A multiple substrate system, a method, and structure for adapting solder volume to a warped module. An illustrative embodiment comprises a method for joining a first substrate to a second substrate. A deviation from a nominal gap between the first substrate and the second substrate at a first region of the first substrate is ascertained. A volume of solder paste necessary to compensate for the deviation from a nominal gap is determined. The volume of solder paste necessary to compensate for the deviation at the first region of the first substrate is applied. Further, the second substrate is bonded to the first substrate using, at least in part, the solder paste applied at the first region of the first substrate.

Abstract: An abutment structure comprises a power rail, a ground rail parallel to the power rail, first cells and second cells. An area is defined between the power and the ground rails. A portion of each first and second cell overlaps the power and the ground rails, and another portion thereof is within the area. The first cells are within the abutment structure with original patterns thereof. The second cells respectively has an original pattern and a base pattern being a flip pattern of the original pattern, and are within the area with alternate of the original and the base patterns. The first and the second cells are within the area alternately without overlapping. Alternatively, the first and the second cells may also be within different areas, and the second cells are within different areas respectively with the base pattern and a flip pattern of the base pattern thereof.

Abstract: A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.

Abstract: The invention relates to a communication apparatus having automatic gain control apparatus and automatic gain control method. It comprises a communication apparatus with automatic gain control apparatus, a signal power calculation apparatus to calculate a first power value of the first digital signal. The operation of gain apparatus is based on the first gain value. The channel status decision apparatus decides the first channel status of the first gain value. The first digital signal has an update period of automatic gain control. The demodulator sends out the first channel impulse response to the automatic gain control apparatus. The channel status decision apparatus adjusts the update period of automatic gain control according to the first channel status of the first digital signal.

Abstract: The invention provides systems and methods for ESD protection for an integrated circuit (IC) having multi-power domains. The IC comprises a first device in a first power domain having a first power line and a first ground line and a second device in a second power domain having a second power line and a second ground line. A clamp circuit having a first node and a second node is coupled to the first device and the second device to provide cross-domain protection. Alternatively, two clamp circuits are used to couple with the first device and the second device to provide cross-domain ESD protection.

Abstract: A method for packaging semiconductor device is provided, which comprises: providing a carrier substrate having a top surface and a back surface, a circuit arrangement on the top surface of the carrier substrate, and a through hole is disposed near the center of the carrier substrate and is formed passed through the carrier substrate; providing a chip having an active surface and a back surface, a plurality of pads is disposed on the periphery of the active surface and a plurality of connecting elements is disposed thereon; the active surface of chip is flipped and bonded on the circuit arrangement on the top surface of the carrier substrate, and the plurality of connecting elements is not covering the through hole; filling the underfilling material to encapsulate between the plurality of connecting elements and the top surface of the carrier substrate and to fill with the through hole; and performing a suction process to remove the air within the underfilling material between the plurality of connecting eleme

Abstract: A device for storing pulse latch with logic circuit and thus having signal maintaining function is provided, wherein the device is composed of a data signal, a scan data input signal, a stored signal, a choosing data input signal, a time clock signal, a restoring signal, a first signal channel, a scan latch, a second signal channel, a pulse latch, a normal output signal, an output signal, a first OR gate, a second OR gate, a third OR gate, a AND gate and an inverter connecting to one another. The device may store the data when being switch off and restore the data when being switch on again.

Abstract: A burn-in socket for carrying an electronic device to let the electronic device electrically connect to a circuit board via the burn-in socket is provided. The electronic device has a body and at least a lead. The burn-in socket comprises a frame and a carrier, the frame has an opening and a plurality of first aligning portions, wherein the opening fits onto the contour of the body, and the first aligning portions surrounds the opening. The carrier has a plurality of second aligning portions. The frame is assembled to the carrier with the conjunction of the first aligning portions and the second aligning portions. The body is capable of fitting into the opening to let the lead electrically connect to the circuit board via the carrier.

Abstract: This invention provides a clock and data recovery system, which comprises a plurality of gm cells, control device, resistor and capacitor. The gm cells respectively have an input end and an output end. The control devices are connected to these output ends. According to a time value, the control device controls a part of the plurality of gm cells to form a first gm cell, and the control device controls another part of the plurality of gm cells to form a second gm cell. The resistor is connected between the first gm cell and the second gm cell. The capacitor is connected to the second gm cell. Wherein, the control device controls the ratio of the first gm cell and the second gm cell in accordance with a time-division multiplexed manner.

Abstract: The present invention provides a method for packaging semiconductor device which is using more than once reflow processes to heat the solder ball to prevent the deformation of solder ball, so that the yield of the manufacturing process can be increased and the reliability of the semiconductor device can be increased.

Abstract: The present invention provides a semiconductor package structure, which includes a substrate having a top surface and a back surface, a plurality of first connecting points on the top surface and a plurality of second connecting points on the back surface; a chip having an active surface and back surface, a plurality of pads on the active surface, and the chip is attached on the top surface of the substrate; a plurality of wires is electrically connected the plurality of pads on the active surface of the chip with the plurality of first connecting points on the top surface of substrate; a first encapsulant is filled to cover portion of the plurality of wires, the chip, and the portion of top surface of the substrate; a second encapsulate is filled to cover the first encapsulant, the plurality of wires and is formed on portion of the top surface of the substrate, in which the Yang's module of the second encapsulant is different with that of the first encapsulant; and a plurality of connecting components is dis

Abstract: The invention creates a slicing level and sampling phase adaptation circuitry for data recovery systems. The invention explores the boundary of the eye opening to decide the optimal slicing level and sampling phase with a simple bit error rate estimation technique. Bit error rate estimation is achieved with several collaborating samplers.

Abstract: A method and a device for multi-channel data alignment in a transmission system are provided, wherein the method comprises receiving a first stream data and a second stream data, determining a deleting/inserting state of the first stream data and the second stream data to generate an information of mismatch data due to a speed difference situation, generating a reverse inserting control signal or a reverse deleting control signal to completely restore the original first stream data and/or the original second stream data at a transmission end, deleting/inserting the first stream data and the second stream data simultaneously after receiving the deleting/inserting state of the first stream data and the second stream data, and outputting the corrected first stream data and the corrected second stream data without mismatching.

Abstract: A through-silicon via (TSV) testing structure is disclosed herein and includes a plurality of controllers, a plurality of transmitters and a plurality of receivers. The controllers are configured to output a first controlling signal and a second controlling signal. The transmitters are respectively connected to the output end of the through-silicon via and one of the controllers, and output a testing output signal in accordance with the first controlling signal and the second controlling signal. The receivers are respectively connected to the input end of the through-silicon via and another one of the controllers, and input a testing input signal in accordance with the first controlling signal and the second controlling signal.

Abstract: The invention discloses a data transfer protection apparatus for a flash memory controller, placed between BCH and NAND Flash Chip. In encode path the hardware module selects a sequence of constant values, exclusive-or the original parity with that constant value. In decode path the hardware module detects the parity period, exclusive-or the parity which is read out from NAND Flash Chip with the same constant value sequence.

Abstract: A programmable current mirror a reference transistor, first and second mirror transistors, and a first current bypass. The reference transistor has a source and a gate coupled to a reference current node. The first and second mirror transistors are coupled together in series at a first node. Each of the first and second mirror transistors having gates coupled to each other and to the gate of the reference transistor. The first current bypass including a switch disposed in parallel with the second mirror transistor. The first current bypass is coupled to a source and a drain of the second mirror transistor and to the first node.

Abstract: A system and method for multi-protocol bus communications between integrated circuits is provided. An electronic system comprises an integrated circuit having an on-chip bus. The integrated circuit includes a master component and a first slave component, both coupled to the on-chip bus and communicate using a first on-chip bus protocol, a slave bus converter coupled to the on-chip bus, and a switch coupled to the slave bus converter and to the on-chip bus. The electronic system further comprising a second slave component coupled to the integrated circuit. The slave bus converter converts bus communications in the first on-chip bus protocol to a second on-chip bus protocol and the switch selectively couples the on-chip bus or the slave bus converter to the second slave component based on a bus select control signal.