Abstract: A phase interpolator including a phase interpolation circuit, a plurality of low pass filtering channels, and a multiplexing circuit is provided. The phase interpolation circuit receives a first clock signal and a second clock signal and accordingly performs an interpolation operation to generate an output clock signal. The low pass filtering channels respectively have an output terminal and an input terminal that is coupled to the phase interpolation circuit to receive the output clock signal. Each of the low pass filtering channels includes a switch and a capacitor which are coupled to a common node as the output terminal. The multiplexing circuit has a plurality of input terminals respectively coupled to the output terminals of the low pass filtering channels. The multiplexing circuit selects an input signal received from one of the low pass filtering channels as a phase interpolation signal according to a selecting signal.

Abstract: An analog-to-digital converter includes comparator modules and an encoder module. Each of the comparator modules is configured to compare a reference voltage with an input signal according to a first clock signal to generate a first comparison signal and a second comparison signal, and to generate a detection signal according to a second clock signal, the first comparison signal, and the second comparison signal. A delay duration is present between the first clock signal and the second clock signal. The encoder module is configured to generate a first bit of digital data according to the first comparison signals from the comparator modules, and to generate a second bit of the digital data according to the detection signals from the comparator modules and the first bit.

Abstract: Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit.

Abstract: A voltage mode transmitter is provided. The voltage mode transmitter includes a control unit and a resistor ladder circuit. The control unit receives a first signal and delays an inverse of the first signal for a time period to obtain a second signal. The resistor ladder circuit is configured to sum up products of the first signal or the second signal and a plurality of weights, thereby generating an output signal. The resistor ladder circuit includes an input terminal, multiple first resistors and a second resistor. The output terminal is configured to output the output signal. Each of the first resistors is coupled between the output terminal and the control unit and receives the first signal or the second signal. The resistances of the first resistors are 2R, 4R . . . and 2nR respectively, where R is a reference resistance. The resistance of the second resistor is 2nR.

Abstract: An integrated circuit includes a main clock tree, a reference clock trunk, a reference clock buffer and a calibration circuit. The main clock tree transmits a main operation clock to an internal node via serially-coupled buffers to form a local clock at an internal node. The reference clock buffer transmits a main reference clock via the reference clock trunk to form a reference clock at a terminal node. The calibration circuit compares phases of the local clock and the reference clock to accordingly generate a control signal, so the main clock tree can adjust phase of the local clock according to the control signal.

Abstract: A method for discrete multitone (DMT) transmission is disclosed. In the method, a DMT signal is received from a transmission channel. The DMT signal is passed through a time-domain equalizer (TEQ) to obtain an equalized DMT signal. The DMT signal is passed through a target impulse response (TIR) filter to obtain a TIR signal. A mean square error (MSE) of an error signal is obtained from the equalized DMT signal and the TIR signal. A TEQ coefficient vector of the TEQ is iteratively updated based on the MSE of the error signal, a frequency kernel matrix corresponding to the TEQ and a frequency kernel matrix corresponding to the TIR filter.

Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a phase interpolator, a finite state machine, and a divisor-controllable frequency divider. The phase detector compares an input data signal with a frequency dividing signal and generates a phase indication signal to indicate a phase difference between the input data signal and the frequency dividing signal. The phase interpolator performs phase interpolation on first and second clock signals received by the phase interpolator, so as to generate a phase interpolation signal. The finite state machine coupled to the phase detector and the phase interpolator generates the control signal based on the phase indication signal and the phase interpolation signal. The divisor-controllable frequency divider coupled to the phase detector and the phase interpolator divides the second frequency of the phase interpolation signal by a divisor so as to generate the frequency dividing signal. A CDR method is also provided.

Abstract: A voltage mode transmitter includes a resistive network and a de-emphasis value controller. The resistive network receives plural input voltages and provides plural weighting values corresponding to respective input voltages. A sum of the products of the plural input voltages and the corresponding weighting values is equal to an output voltage. The de-emphasis value controller receives a first signal. After the first signal is inverted as an inverted first signal and the inverted first signal is delayed for a time period, the de-emphasis value controller generates a second signal. The de-emphasis value controller further receives a value control signal. At least one of the plural input signals is provided by the first signal and at least one of the plural input signals is provided by the second signal according to the value control signal.

Abstract: A receiver is provided. The receiver includes a CTLE receiving a received signal, and generating a first equalized signal by processing the received signal according to a pole and a boost level; a slicing circuit coupled to the CTLE, generating a data signal according to the first equalized signal and a feedback equalization signal; a DFE coupled to the slicing circuit, generating the feedback equalization signal by processing the data signal according to a DFE coefficient set. Furthermore, the boost level is adjusted according to a first DFE coefficient of the DFE coefficient set, while the pole is adjusted according to the second and third DFE coefficients.

Abstract: A clock and data recovery circuit includes a sampling module, a phase detect module, a parallel-to-serial converter and a phase adjust module. The sampling module generates a data signal and an edge signal according to input data, a first clock signal and a second clock signal. The phase detect module detects a phase of the data signal and a phase of the edge signal to generate first output recovered data and a first phase adjust signal. The parallel-to-serial converter performs a parallel-to-serial conversion on the first recovered data and the first phase adjust signal, so as to generate second output recovered data and a second phase adjust signal. The phase adjust module generates the first clock signal and the second clock signal, and adjusts the first clock signal and the second clock signal according to the second output recovered data and the second phase adjust signal.

Abstract: A receiver circuit including an external terminal, a level shifter, a reset circuit, and an inverting circuit is provided. The external terminal receives the external signal. The level shifter shifts a voltage swing range of the external signal to generate a level shifting signal. The level shifter includes a pull-up unit and a pull-down unit coupled in series. The pull-up unit and the pull-down unit are alternatively switched respectively according to the external signal and the internal signal, and thus a leakage path of the level shifter is cut off for different states of the external signal. The reset circuit couples the external terminal and the level shifter and provides a reset path according to the external signal for assisting the switching of the pull-up unit and the pull-down unit. The inverting circuit couples the level shifter and inverts the level shifting signal to generate the internal signal.

Abstract: A clock data recovery system is provided. A CTLE generates a first equalized signal. An adder superposes the first equalized signal and a feedback equalization signal and generates a superposed signal. A first error slicer slices the superposed signal according to a clock signal and a reference voltage and generates a first error signal. A second error slicer slices the superposed signal according to the clock signal and a second slicing voltage. A data slicer slices the superposed signal according to the clock signal and a third slicing voltage and generates a data signal. A CDR circuit generates the clock signal. An adaptive filter receives the data signal and the first error signal, and generates the reference voltage and a DFE coefficient set. A DFE receives the data signal and the DFE coefficient set, and generates the feedback equalization signal.

Abstract: A squelch detector receives a first input signal, a second input signal, a first reference voltage and a second reference voltage. The first input signal and the second input signal are collaboratively defined as a differential input signal pair. The difference between the first reference voltage and the second reference voltage is defined as a squelch threshold. According to the squelch threshold, the squelch detector generates a detected signal to indicate whether the differential input signal pair is valid or not.

Abstract: An apparatus is provided. A first adder generates a first superposed signal in response to a first feedback equalization signal and an input signal. A second adder generates a second superposed signal in response to a second feedback equalization signal and the first superposed signal. An edge slicer generates an edge signal by slicing the first superposed signal. A data slicer generates a data signal by slicing the second superposed signal. An error slicer generates an error signal by slicing the second superposed signal. A CDR circuit generates a first and second clock signal in response to the data signal and the edge signal. An adaptive filter generates the reference signal and equalizer coefficients in response to data signal and the error signal. An equalizing unit generates the first feedback equalization signal and the second feedback equalization signal in response to the data signal and the equalizer coefficients.

Abstract: A silicon controlled rectifier includes a substrate, a well, a deep doped region, a first doped region, a second doped region, a third doped region, and a fourth doped region. The well is disposed on the substrate and underneath a cell region. The deep doped region is disposed in the well. The first doped region has a first conductivity type, and is disposed in the well. The second doped region and third doped region have the first conductivity type and are disposed on the deep doped region. The fourth doped region has a second conductivity type, and is disposed between the second doped region and the third doped region. The fourth doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region, the second doped region, and the third doped region.

Abstract: A squelch detector receives a first input signal, a second input signal VM, a first reference voltage and a second reference voltage. The first input signal and the second input signal are collaboratively defined as a differential input signal. The difference between the first reference voltage and the second reference voltage is defined as a squelch threshold. According to the squelch threshold, the squelch detector generates a detected signal to indicate whether the differential input signal is valid.

Abstract: An active inductor includes a first transistor, a capacitor, a second transistor, a first resistor, a second resistor, and a bias current source. A source terminal of the first transistor is a first terminal of the active inductor and connected to a first voltage source. The capacitor is connected to the source terminal and gate terminal of the first transistor. A drain terminal of the second transistor is connected to the source terminal of the first transistor. A gate terminal of the second transistor is connected to a drain terminal of the first transistor. The first resistor is connected between the drain terminal of the first transistor and a second terminal of the active inductor. The second resistor is connected to a source terminal of the second transistor. The bias current source is connected between the second resistor and a second voltage source.

Abstract: Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit.

Abstract: A multi-channel transceiver includes a phase-locked loop circuit, a first transmitting channel and a second transmitting channel. The phase-locked loop circuit generates a first clock signal set and a second clock signal set with different frequencies. The first transmitting channel includes a first phase adjusting circuit and a first transmitter. The first phase adjusting circuit receives the first clock signal set and generates a first spread spectrum clock signal with a first SSCG profile. According to the first spread spectrum clock signal, the first transmitter generates a first serial data. The second transmitting channel includes a second phase adjusting circuit and a second transmitter. The second phase adjusting circuit receives the second clock signal set and generates a second spread spectrum clock signal with a second SSCG profile. According to the second spread spectrum clock signal, the second transmitter generates a second serial data.

Abstract: An abutment structure comprises a power rail, a ground rail parallel to the power rail, first cells and second cells. An area is defined between the power and the ground rails. A portion of each first and second cell overlaps the power and the ground rails, and another portion thereof is within the area. The first cells are within the abutment structure with original patterns thereof. The second cells respectively has an original pattern and a base pattern being a flip pattern of the original pattern, and are within the area with alternate of the original and the base patterns. The first and the second cells are within the area alternately without overlapping. Alternatively, the first and the second cells may also be within different areas, and the second cells are within different areas respectively with the base pattern and a flip pattern of the base pattern thereof.