Patents Assigned to Global Unichip Corporation
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Patent number: 8816708Abstract: Electronic test system and associated method, including a first and a second connection terminals respectively coupled to two pins of a chip under test, a signal source terminal coupled to a signal generator, a first and a second measurement terminals coupled to a tester, a fifth switch, a seventh switch and a switch circuit which has a first and a fourth front terminals coupled to the signal source terminal, has a first and a fourth back terminals coupled to the first and second connection terminals, and controls conduction between the first front terminal and the first back terminal, as well as conduction between the fourth front terminal and the fourth back terminal. The fifth switch is coupled between the fourth back terminal and the first measurement terminal, and the seventh switch is coupled between the first connection terminal and the second measurement terminal.Type: GrantFiled: July 12, 2012Date of Patent: August 26, 2014Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., LtdInventors: Shin-Cheng Chu, Ching-Tsung Chen, Teng-Hui Lee, Chia-Jen Kao
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Patent number: 8779739Abstract: A DC converter is provided for converting a first supply voltage into a second supply voltage. The first supply voltage is higher than the second supply voltage. The DC converter includes a driving stage and an output stage. The driving stage includes a modulation circuit, a pull-up driving unit, a pull-up unit, a pull-down driving unit, and a pull-down unit. The modulation circuit generates a control signal according to the second supply voltage. The pull-up driving unit generates a first P-type driving signal and a second P-type driving signal to the pull-up unit according to the control signal. The pull-down driving unit generates a first N-type driving signal and a second N-type driving signal to the pull-down unit according to the control signal.Type: GrantFiled: February 5, 2013Date of Patent: July 15, 2014Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yen Huang, Jung-Tsun Chuang
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Publication number: 20140152364Abstract: Phase offset cancellation circuit and associated clock generator, include a first modifying phase interpolator and a second modifying phase interpolator, and provide a first modified clock and a second modified clock according to a first to a fourth input clocks; wherein the first and the third clocks are of opposite phases. The first modifying phase interpolator performs equal phase interpolation between the first and the second input clocks to generate the first modified clock, and the second modifying phase interpolator performs equal phase interpolation between the third and the fourth input clocks to generate the second modified clock, such that a phase difference between the first modified clock and the second modified clock is of substantially 90 degrees, against phase offsets between the first to the fourth input clocks.Type: ApplicationFiled: November 27, 2013Publication date: June 5, 2014Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventor: Chen-Yang Pan
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Patent number: 8744832Abstract: A hybrid electronic design system and a reconfigurable connection matrix thereof are disclosed. The electronic design system includes a virtual unit, a hybrid unit and a communication channel. The virtual unit further includes a plurality of proxy units, a plurality of virtual components and a driver. The virtual components are connected with the driver via the proxy units. The hybrid unit further includes an emulate unit, a physical unit and a chip level transactor. The chip level transactor is connected with the emulate unit and the physical unit. The communication channel is connected with the driver of the virtual unit and the chip level transactor of the hybrid unit.Type: GrantFiled: December 21, 2010Date of Patent: June 3, 2014Assignee: Global Unichip CorporationInventor: Peisheng Alan Su
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Patent number: 8724269Abstract: ESD protection circuit is provided, which includes a detection circuit, a trigger circuit and a clamp circuit. The detection circuit includes two stacked capacitors reflecting occurrence of ESD events. The trigger circuit includes three stacked transistors controlling triggering of the clamp circuit according to operation of the detection circuit. The clamp circuit includes two stacked transistors conducting ESD path when triggered.Type: GrantFiled: January 18, 2012Date of Patent: May 13, 2014Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Tai Wang, Sheng-Tsai Huang, Chao-Yen Huang
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Publication number: 20140103965Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.Type: ApplicationFiled: December 16, 2013Publication date: April 17, 2014Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventors: Wen-Tai Wang, Chao-Yen Huang
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Publication number: 20140103966Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.Type: ApplicationFiled: December 16, 2013Publication date: April 17, 2014Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventors: Wen-Tai Wang, Chao-Yen Huang
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Patent number: 8669803Abstract: A high speed level shifter is provided for converting a low input voltage into a wide-range high output voltage. By utilizing two switching units to improve the latching speed of the latching unit of the level shifter, the duty cycle of the input signal is nearly equal to the duty cycle of the output signal.Type: GrantFiled: February 21, 2013Date of Patent: March 11, 2014Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yen Huang, Jung-Tsun Chuang
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Patent number: 8633737Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.Type: GrantFiled: March 1, 2012Date of Patent: January 21, 2014Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., LtdInventors: Wen-Tai Wang, Chao-Yen Huang
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Patent number: 8593215Abstract: The invention discloses a power gating for in-rush current mitigation. Firstly the circuit uses small power switch cells at first stage, such that those power switch cells run in saturation region. Secondly a delay unit delays a switch signal to control the dwell time of current to reduce the peak value of the current. Thirdly large power switch cells are used at the rest, such that those power switch cells operate in linear region.Type: GrantFiled: January 20, 2012Date of Patent: November 26, 2013Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company LimitedInventor: Shih-Hao Chen
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Publication number: 20130283221Abstract: Method for input/output (IO) design of a chip, including: according to a signal IO pin sequence and associated driving parameters, sequentially placing a signal IO cell in the IO design associated with each of the signal IO pins; after a signal IO cell is placed, performing a simultaneous switching output (SSO) verification step according to physical layout parameters and locations of the signal IO cells placed in the IO design, so as to check whether an SSO specification is violated; if not violated, continuing to place a signal IO cell of a next signal IO pin; if violated, including a decoupling capacitor, an IO power cell and/or an IO ground cell in the IO design.Type: ApplicationFiled: April 16, 2013Publication date: October 24, 2013Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventors: Shi-Hao Chen, Tsung-Ying Tsai, Chao-Yen Huang
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Publication number: 20130272358Abstract: Eye diagram scan circuit and associated method for a receiver circuit, including a level adjust circuit, a phase interpolator and a control module. The receiver circuit provides a first data signal and a primary phase data according to a received signal. The control module provides a phase offset data and a level offset data. The level adjust circuit adjusts a level of the received signal in respond to the level offset data; the phase interpolator triggers according to a sum of the phase offset data and the primary phase data, so a second data signal is provide in response to the level-adjusted received signal. The control module compares the first data signal and the second data signal, and accordingly provides an eye diagram scan result for the phase offset data and the level offset data.Type: ApplicationFiled: April 16, 2013Publication date: October 17, 2013Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventors: Liang-Hung Chen, Yen-Chung Chen, Jung-Chi Huang
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Patent number: 8547149Abstract: This invention provides a clock and data recovery system, which comprises a plurality of gm cells, control device, resistor and capacitor. The gm cells respectively have an input end and an output end. The control devices are connected to these output ends. According to a time value, the control device controls a part of the plurality of gm cells to form a first gm cell, and the control device controls another part of the plurality of gm cells to form a second gm cell. The resistor is connected between the first gm cell and the second gm cell. The capacitor is connected to the second gm cell. Wherein, the control device controls the ratio of the first gm cell and the second gm cell in accordance with a time-division multiplexed manner.Type: GrantFiled: March 30, 2011Date of Patent: October 1, 2013Assignee: Global Unichip CorporationInventors: Fu-Tai An, Jen-Tai Hsu, Yi-Lin Lee
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Patent number: 8518722Abstract: A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.Type: GrantFiled: March 9, 2011Date of Patent: August 27, 2013Assignee: Global Unichip CorporationInventors: Chien-Wen Chen, Chia-Jen Kao, Jui-Cheng Chuang
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Publication number: 20130214838Abstract: A high speed level shifter is provided for converting a low input voltage into a wide-range high output voltage. By utilizing two switching units to improve the latching speed of the latching unit of the level shifter, the duty cycle of the input signal is nearly equal to the duty cycle of the output signal.Type: ApplicationFiled: February 21, 2013Publication date: August 22, 2013Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventors: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
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Publication number: 20130214749Abstract: A DC converter is provided for converting a first supply voltage into a second supply voltage. The first supply voltage is higher than the second supply voltage. The DC converter includes a driving stage and an output stage. The driving stage includes a modulation circuit, a pull-up driving unit, a pull-up unit, a pull-down driving unit, and a pull-down unit. The modulation circuit generates a control signal according to the second supply voltage. The pull-up driving unit generates a first P-type driving signal and a second P-type driving signal to the pull-up unit according to the control signal. The pull-down driving unit generates a first N-type driving signal and a second N-type driving signal to the pull-down unit according to the control signal.Type: ApplicationFiled: February 5, 2013Publication date: August 22, 2013Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventors: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.
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Patent number: 8487642Abstract: A burn-in socket for carrying an electronic device to let the electronic device electrically connect to a circuit board via the burn-in socket is provided. The electronic device has a body and at least a lead. The burn-in socket comprises a frame and a carrier, the frame has an opening and a plurality of first aligning potions, wherein the opening fits onto the contour of the body, and the first aligning portions surrounds the opening. The carrier has a plurality of second aligning portions. The frame is assembled to the carrier with the conjunction of the first aligning portions and the second aligning portions. The body is capable of fitting into the opening to let the lead electrically connect to the circuit board via the carrier.Type: GrantFiled: November 23, 2010Date of Patent: July 16, 2013Assignee: Global Unichip CorporationInventors: Yu-Min Sun, Chih-Feng Cheng
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Patent number: 8487645Abstract: A through-silicon via (TSV) testing structure is disclosed herein and includes a plurality of controllers, a plurality of transmitters and a plurality of receivers. The controllers are configured to output a first controlling signal and a second controlling signal. The transmitters are respectively connected to the output end of the through-silicon via and one of the controllers, and output a testing output signal in accordance with the first controlling signal and the second controlling signal. The receivers are respectively connected to the input end of the through-silicon via and another one of the controllers, and input a testing input signal in accordance with the first controlling signal and the second controlling signal.Type: GrantFiled: February 23, 2011Date of Patent: July 16, 2013Assignee: Global Unichip CorporationInventors: Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng
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Patent number: 8488731Abstract: The invention creates a slicing level and sampling phase adaptation circuitry for data recovery systems. The invention explores the boundary of the eye opening to decide the optimal slicing level and sampling phase with a simple bit error rate estimation technique. Bit error rate estimation is achieved with several collaborating samplers.Type: GrantFiled: February 1, 2011Date of Patent: July 16, 2013Assignee: Global Unichip CorporationInventors: Fu-Tai An, Jen-Tai Hsu
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Patent number: 8473793Abstract: A boundary scan circuit containing a freeze circuit and a transparency circuit that provides a capability to selectively place portions of a system logic in a sleep mode and thereby conserving power. There are two transparency circuit configurations, one that connects to an input pad cell and one that connects to an output pad cell. The circuitry in the transparency circuit is controlled in such a manner as to establish at the output of transparency circuit a known logic state to control leakage current resulting from the circuitry of the various pad cell configurations, which further conserves power during sleep mode.Type: GrantFiled: June 10, 2010Date of Patent: June 25, 2013Assignee: Global Unichip CorporationInventor: Min-Hsiu Tsai