Patents Assigned to GLOBALFOUNDRIES Singapore Pte. Ltd.
  • Patent number: 11355599
    Abstract: Methods of forming a ferroelectric material layer below a field plate for achieving increased Vbr with reduced Rdson and resulting devices are provided. Embodiments include forming a N-Drift in a portion of the Si layer formed in a portion of a p-sub; forming an oxide layer over portions of the Si layer and the N-Drift; forming a gate over a portion of the oxide layer; forming a S/D extension region in the Si layer; forming first and second spacers on opposite sides of the gate and the oxide layer; forming a S/D region in the Si layer adjacent to the S/D extension region and a S/D region in the N-Drift remote from the Si layer; forming a U-shaped ferroelectric material layer over the oxide layer and the N-Drift, proximate or adjacent to the gate; and filling the U-shaped ferroelectric material layer with a metal, a field gate formed.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: June 7, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Kiok Boone Quek
  • Patent number: 11349071
    Abstract: A memory device may include at least one inert electrode, at least one active electrode, an insulating element arranged at least partially between the at least one active electrode and the at least one inert electrode, and a switching element arranged under the insulating element. The switching element may be arranged at least partially between the at least one active electrode and the at least one inert electrode. The switching element may include a first end and a second end contacting the at least one active electrode; and a middle segment between the first end and the second end, where the middle segment may at least partially contact the at least one inert electrode.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: May 31, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Shyue Seng Tan, Steven Soss
  • Patent number: 11335852
    Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a dielectric layer having an opening, sidewalls along the opening, a first electrode in the opening, a resistive layer disposed upon the first electrode, an oxygen scavenging layer disposed upon the resistive layer, and a second electrode in contact with the oxygen scavenging layer. The oxygen scavenging layer includes a material that is different from the resistive layer and partially covers the resistive layer. The first electrode is electrically linked to the second electrode by the oxygen scavenging layer and the resistive layer.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 17, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Shyue Seng Tan
  • Patent number: 11335635
    Abstract: A semiconductor device is provided. A semiconductor device includes a first and a second region, a dielectric layer, a capping layer, and a planar resistive layer. The dielectric layer is arranged over the first and second regions and the capping layer is arranged over the dielectric layer. The capping layer has a substantially planar top surface over the first and second regions. The planar resistive layer is encapsulated within the capping layer in the first device region.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: May 17, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Benfu Lin, Kah Wee Gan, Cing Gie Lim, Chengang Feng
  • Patent number: 11327045
    Abstract: A sensor device includes a substrate, first and second source regions, first and second drain regions, first and second channel regions, and first and second gate structures disposed over the first and second channel regions respectively. The source regions and drain regions are at least partially disposed within the substrate. The second gate structure includes first and second gate elements, and a resistance region configured to provide a resistance to a second current flow through the second channel region. In use, the first gate structure may receive a solution, and a change in pH in the solution changes a first current flow through the first channel region. In turn, the second current flow through the second channel region changes to compensate for the change in the first current flow to maintain a constant current flow through the sensor device.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 10, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lanxiang Wang, Ping Zheng, Shyue Seng Tan, Eng Huat Toh
  • Patent number: 11320417
    Abstract: In a non-limiting embodiment, a device may include a substrate having conducting lines thereon. One or more fin structures may be arranged over the substrate. Each fin structure may include a sensor arranged over the substrate and around the fin structure. The sensor may include a self-aligned first sensing electrode and a self-aligned second sensing electrode arranged around the fin structure. The first sensing electrode and the second sensing electrode each may include a first portion lining a sidewall of the fin structure and a second portion arranged laterally from the first portion. At least the first portion of the first sensing electrode and the first portion of the second sensing electrode may define a sensing cavity of the sensor. The second portion of the first sensing electrode and the second portion of the second sensing electrode may be electrically coupled to the conducting lines.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 3, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Eng Huat Toh, Kiok Boone Elgin Quek
  • Patent number: 11316063
    Abstract: According to various embodiments, there is provided a diode device including a semiconductor substrate of a first conductivity type, a first semiconductor region formed within the semiconductor substrate, an epitaxial region of the first conductivity type, and a second semiconductor region of a second conductivity type different from the first conductivity type. The first semiconductor region includes a chalcogen. The epitaxial region is formed over the first semiconductor region. The second semiconductor region is formed over the epitaxial region.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 26, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sandipta Roy, Khee Yong Lim, Lanxiang Wang, Kiok Boone Elgin Quek, Jing Hua Michelle Tng
  • Patent number: 11313827
    Abstract: According to various embodiments, there is provided a sensor device that includes: a substrate and two semiconductor structures. Each semiconductor structure includes a source region and a drain region at least partially disposed within the substrate, a channel region between the source region and the drain region, and a gate region. A first semiconductor structure of the two semiconductor structures further includes a sensing element electrically connected to the first gate structure. The sensing element is configured to receive a solution. The drain regions of the two semiconductor structures are electrically coupled. The source regions of the two semiconductor structures are also electrically coupled. A mobility of charge carriers of the channel region of a second semiconductor structure of the two semiconductor structures is lower than a mobility of charge carriers of the channel region of the first semiconductor structure.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 26, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lanxiang Wang, Bin Liu, Eng Huat Toh, Shyue Seng Tan, Kiok Boone Elgin Quek
  • Patent number: 11315876
    Abstract: A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: April 26, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Xuesong Rao, Yun Ling Tan, Yudi Setiawan, Siow Lee Chwa
  • Patent number: 11309324
    Abstract: An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive word line structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive word line structure is shared by the first and second memory cells.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: April 19, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yongshun Sun, Eng Huat Toh, Shyue Seng Tan, Kiok Boone Elgin Quek
  • Patent number: 11302702
    Abstract: Structures for a non-volatile memory and methods of forming such structures. A gate electrode and a gate dielectric layer are formed over an active region with the gate dielectric layer between the gate electrode and the active region. A first doped region is formed in the active region, a second doped region is formed in the active region, and a source line is coupled to the second doped region. The first doped region is positioned in the active region at least in part beneath the gate dielectric layer, and the second doped region is positioned in the active region adjacent to the first doped region. The first doped region has a first conductivity type, and the second doped region has a second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: April 12, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Sriram Balasubramanian, Shyue Seng Tan
  • Patent number: 11302687
    Abstract: A semiconductor device includes a substrate; a collector including a buried layer within the substrate, a first well region over a first portion of the buried layer, and a first conductivity region at least partially within the first well region; a base including a second well region over a second portion of the buried layer and laterally adjacent to the first well region, and a second conductivity region at least partially within the second well region; an emitter including a third conductivity region at least partially within the second conductivity region; an isolation element between the first and the third conductivity regions; a conductive plate on the isolation element and electrically connected with the first conductivity region. The buried layer, the first well region, the first and the third conductivity regions have a first conductivity type; the second well region and the second conductivity region have a second conductivity type.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 12, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jie Zeng, Raunak Kumar
  • Patent number: 11289649
    Abstract: Structures for a non-volatile memory element and methods of forming a structure for a non-volatile memory element. A switching layer is positioned over a first electrode, and a dielectric layer is positioned over the switching layer. The dielectric layer includes an opening extending to the switching layer. A second electrode includes a portion in the opening in the dielectric layer. The portion of the second electrode is in contact with a first portion of the switching layer. The switching layer further includes a second portion positioned between the dielectric layer and the first electrode.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: March 29, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Lup San Leong, Curtis Chun-I Hsieh, Juan Boon Tan, Eng Huat Toh, Kin Wai Tang
  • Patent number: 11282953
    Abstract: According to various embodiments, a transistor device may include a substrate. The transistor device may further include a drain terminal and a source terminal formed in the substrate, and a gate terminal formed over the substrate. The transistor device may further include an insulator structure arranged between the drain terminal and the source terminal, and at least partially under the gate terminal. The insulator structure may include an oxide member and a trench isolation region. The oxide member may be at least partially formed over the trench isolation region.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: March 22, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ming Li, Sivaramasubramaniam Ramasubramaniam, Dong Hyun Shin, Di Wu, Yunpeng Xu, Chenji Zou, Jeoung Mo Koo
  • Patent number: 11276460
    Abstract: Structures for an optoelectronic memory and related fabrication methods. A metal oxide layer is located on an interlayer dielectric layer. A layer composed of a donor/acceptor dye is positioned on a portion of the first layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: March 15, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Jianxun Sun, Juan Boon Tan, Tu Pei Chen, Eng Huat Toh
  • Patent number: 11270938
    Abstract: A semiconductor device may be provided, including a base layer, an insulating layer arranged over the base layer, a memory structure arranged at least partially within the insulating layer, where the memory structure may include a first electrode, a second electrode, and an intermediate element between the first electrode and the second electrode, and a resistor arranged at least partially within the insulating layer, where the resistor may be arranged in substantially a same horizontal plane with one of the first electrode and the second electrode.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: March 8, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Kai Kang, Yi Jiang, Curtis Chun-I Hsieh, Wanbing Yi, Juan Boon Tan
  • Patent number: 11271082
    Abstract: The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure provides a semiconductor device including an isolation region disposed on a substrate, a pair of diffusion structures disposed upon the isolation region, a dielectric layer that covers side surfaces of the diffusion structures, and a gate structure disposed on the dielectric layer and between the diffusion structures, where the gate structure is electrically coupled to the diffusion structures.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: March 8, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Wei Chang, Eng Huat Toh, Shyue Seng Tan
  • Patent number: 11257949
    Abstract: An LDMOS transistor device may be provided, including a substrate having a conductivity region arranged therein, a first isolation structure arranged within the substrate, a source region and a drain region arranged within the conductivity region, a second isolation (local isolation) structure arranged between the source region and the drain region, and a gate structure arranged at least partially within the second isolation structure. The first isolation structure may extend along at least a portion of a border of the conductivity region, and a depth of the second isolation structure may be less than a depth of the first isolation structure. In use, a channel for electron flow may be formed along at least a part of a side of the gate structure arranged within the second isolation (local isolation) structure.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: February 22, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Bong Woong Mun, Jeoung Mo Koo
  • Patent number: 11257808
    Abstract: A method of forming a LDMOS with a self-aligned P+ implant and LVPW region at the source side and the resulting device are provided. Embodiments include forming a DNWELL in a p-sub; forming a PWHV in the DNWELL; forming an NW in the DNWELL; forming a LVPW in the PWHV; forming STI structures through the LVPW and through the DNWELL and NW, respectively; forming a gate over the PWHV; forming a first and a second P+ implant in the LVPW, an edge of the second P+ implant aligned with an edge of the gate; forming a first N+ implant in the LVPW between the first STI structure and the second P+ implant and a second N+ in the NW adjacent to the second STI structure; and forming contacts over the first and second P+ and N+ implants, respectively, and an electrical contact over the second N+ implant.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: February 22, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yohann Frederic Michel Solaro, Vvss Satyasuresh Choppalli, Chai Ean Gill
  • Patent number: 11251095
    Abstract: An analog high gain transistor is disclosed. The formation of the analog high gain transistor is highly compatible with existing CMOS processes. The analog high gain transistor includes a double well, which includes the well implants of the low voltage (LV) and intermediate voltage (IV) transistors. In addition, the analog high gain transistor includes light doped extension regions of IV transistor and a thin gate dielectric of the LV transistor.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: February 15, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Yuan Sun, Shyue Seng Jason Tan