Patents Assigned to GLOBALFOUNDRIES Singapore Pte. Ltd.
  • Patent number: 10724983
    Abstract: A sensor device may include a substrate, first and second source regions, first and second drain regions, first and second channel regions, and first and second gate structures disposed over the first and second channel regions, respectively. The source regions and drain regions may be at least partially disposed within the substrate. The first and second source regions may have first and second source resistances, respectively, and the second source resistance may be higher than the first source resistance. The first gate structure may receive a solution, and a change in pH in the solution may cause a change in a first current flow through the first channel region. In turn, the second current flow through the second channel region may change to compensate for the change in the first current flow to maintain a constant current flow through the sensor device.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Bin Liu, Eng Huat Toh, Shyue Seng Tan, Ming Tsang Tsai, Khee Yong Lim, Kiok Boone Elgin Quek
  • Patent number: 10720513
    Abstract: Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 21, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Kiok Boone Quek
  • Patent number: 10720580
    Abstract: A device including a reduced top RRAM electrode structure, and method of production thereof. Embodiments include a bottom resistive random-access memory (RRAM) electrode structure over a plurality of lower metal level contacts formed laterally separated in a substrate; a resistive switching structure over the bottom RRAM electrode structure; a top RRAM electrode structure over the resistive switching structure; a protective structure over the top RRAM electrode structure; an encapsulation structure over the bottom RRAM electrode structure and on sidewalls of the resistive switching structure, the top RRAM electrode structure and the protective structure; and an Nblock layer over the substrate.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 21, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Wanbing Yi, Yi Jiang, Juan Boon Tan
  • Patent number: 10707358
    Abstract: A semiconductor device having a substrate with at least one photo-detecting region and at least one bond pad is provided. A first passivation layer is deposited over the substrate and over step portions at the edges of the bond pad and a trench having sidewalls and a bottom surface is formed in the substrate. A light shielding layer is deposited over the first passivation layer and covering the trench sidewalls. The light shielding layer has end portions at the photo-detecting region, at step portions at the edges of the bond pad and at the bottom surface of the trench. A second passivation layer is deposited over the light shielding layer. A third passivation layer is deposited over the end portions of the light shielding layer at the photo-detecting region and at the step portions at edges of the bond pad.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Juan Boon Tan, Kiok Boone Elgin Quek, Khee Yong Lim, Chim Seng Seet, Rajesh Nair
  • Patent number: 10707408
    Abstract: Methods of forming a high sensitivity Hall effect sensor having a thin Hall plate and the resulting devices are provided. Embodiments include providing a SOI substrate having a sequentially formed Si substrate and BOX and Si layers; forming a first STI structure in a first portion of the Si layer above the BOX layer, the first STI structure having a cross-shaped pattern; forming a second STI structure in a frame-shaped pattern in a second portion of the Si layer; the second STI structure formed outside and adjacent to the first STI structure; removing a portion of the Si layer between the first and second STI structures down to the BOX layer; removing the first STI structure, a cross-shaped Si layer remaining; and implanting N+ dopant ions into each end of the cross-shaped Si layer to form N+ implantation regions.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shyue Seng Tan, Eng Huat Toh
  • Patent number: 10700277
    Abstract: A memory device may include a bottom electrode, first and second switching elements over the bottom electrode, and first and second top electrodes over the first and second switching elements respectively. The first and second top electrodes may include first and second contact surfaces in contact with the first and second switching elements respectively. The first and second switching elements may each have a resistance configured to switch between resistance values in response to changes in voltages applied between the top electrodes and the bottom electrode. The bottom electrode may include at least one conductive layer having third and fourth contact surfaces in contact with the first and second switching elements respectively. An area of the first contact surface may be greater than an area of the third contact surface, and an area of the second contact surface may be greater than an area of the fourth contact surface.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lanxiang Wang, Shyue Seng Tan, Eng Huat Toh
  • Patent number: 10693445
    Abstract: Provided are integrated circuits that include one or more magnetic tunnel junction ring oscillator(s) with tunable frequency and methods for operating the same. Accordingly, an integrated circuit is provided that includes a ring oscillator. The ring oscillator includes an input voltage terminal, an output voltage terminal, and an odd number of at least three inverters disposed electrically in series with one another between the input voltage terminal and the output voltage terminal. Each of the at least three inverters includes an NMOS transistor and one or more magnetic tunnel junctions (MTJs) disposed electrically in series with the NMOS transistor. The NMOS transistor of each of the at least three inverters is selectively tunable with regard to either or both of its threshold voltage and its effective channel width.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bin Liu, Eng Huat Toh
  • Patent number: 10692920
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a photodetector, where the photodetector includes an impingement photodetector well and a base photodetector well. A transfer transistor overlies the photodetector, where the transfer transistor includes a transfer gate, a source, and a drain. A source contact is electrically connected to the source, and the source contact is also electrically connected to the photodetector.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ping Zheng, Eng Huat Toh
  • Patent number: 10693054
    Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Wanbing Yi, Curtis Chun-I Hsieh, Yi Jiang, Juan Boon Tan, Benfu Lin
  • Patent number: 10685970
    Abstract: A method of forming a low-cost and compact hybrid SOI and bulk MTP cell and the resulting devices are provided. Embodiments include forming a bulk region in a SOI wafer; forming an NW in the bulk region and a PW in a remaining SOI region of the SOI wafer; forming first and second pairs of common FG stacks over both of the SOI and bulk regions; forming a first shared N+ RSD between each common FG stack of the first and second pairs in a top Si layer; forming a N+ RSD in the top Si layer of the SOI region on an opposite side of each common FG stack from the first shared N+ RSD; forming a second shared N+ RSD between each common FG stack in the bulk region; and forming a P+ RSD between the first and second pairs in the bulk region.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Danny Pak-Chum Shum
  • Patent number: 10686008
    Abstract: Methods of magnetically shielding an MRAM structure on all six sides in a thin wire or thin flip chip bonding package and the resulting devices are provided. Embodiments include forming a first metal layer embedded between an upper and a lower portion of a PCB substrate, the first metal layer having a pair of metal filled vias laterally separated; attaching a semiconductor die to the upper portion of the PCB substrate between the pair of metal filled vias; connecting the semiconductor die electrically to the PCB substrate through the pair of metal filled vias; removing a portion of the upper portion of the PCB substrate outside of the pair of metal filled vias down to the first metal layer; and forming a second metal layer over and on four opposing sides of the semiconductor die, the second metal layer landed on the first metal layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shan Gao, Boo Yang Jung
  • Patent number: 10680099
    Abstract: A transistor, such as laterally diffused (LD) transistor, having a band region below a drift well is disclosed. The band region and drift well are oppositely doped. The band region is self-aligned to the drift well. The band region reduces the depth of the drift well. A shallower drift well reduces risk of punch-through, improving reliability. In addition, the shallower drift well reduces the drain to body parasitic capacitance which improves performance.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: June 9, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Liming Li, Shaoqiang Zhang, Ruchil Kumar Jain, Raj Verma Purakh
  • Patent number: 10656362
    Abstract: Devices with gamma (?) grooves are disclosed. The ? grooves can be used to form optical fiber arrays. The ? grooves can be formed using a dry etch, such as RIE, by modifying resist features of an etch mask to have convex curved sidewalls. The profile of the resist features is transferred to the substrate by the dry etch to form the ? grooves. The ? grooves are formed without K containing etchants, avoiding K+ ions contamination of process tools as well as health issues caused by handling alkali containing devices.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yamin Huang, Bo Liu, Zhihong Mai, Jeffrey C Lam
  • Patent number: 10658505
    Abstract: A high voltage device may include a substrate, source and drain regions, a gate structure and an oxide layer. The substrate may include a recessed region with a recessed surface lower than a top surface of the substrate. The source and drain regions may be at least partially arranged within the substrate under the recessed surface and top surface respectively. The drain region may be positioned higher than the source region. The gate structure may include first and second portions arranged over the recessed region. The first and second portions may be nearer to the source and drain regions respectively. The oxide layer may include a first part between the first portion of the gate structure and the recessed surface, and a second part between the second portion of the gate structure and the recessed surface. The second part of the oxide layer may be thicker than the first part.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Guowei Zhang
  • Patent number: 10658316
    Abstract: According to an aspect of the present disclosure, a semiconductor device is provided that includes a substrate, at least one bond pad, a passivation layer and a NBLoK layer. The bond pad is formed over the substrate. The passivation layer is deposited over the substrate and has an opening defined by end portions of the passivation layer over the bond pad. The NBLoK layer is covering the end portions of the passivation layer.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xiaodong Li, Juan Boon Tan, Ramasamy Chockalingam
  • Patent number: 10651380
    Abstract: In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region. A base dielectric layer is arranged over the substrate. The base dielectric layer includes an interconnect in the first region. A first electrode is arranged over the interconnect in the first region. A mask structure is arranged over the first electrode. At least one spacer stack is arranged at least partially around the mask structure and the first electrode. The spacer stack(s) includes a resistive switching element at least partially lining sidewalls of the mask structure and the first electrode, and a second electrode arranged over the resistive switching element.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Wanbing Yi, Yi Jiang, Juan Boon Tan
  • Patent number: 10651238
    Abstract: Multi-time programmable (MTP) random access memory (RRAM) devices and methods for forming a MTP RRAM device are disclosed. The method includes providing a substrate. The substrate is prepared with at least a first region for accommodating one or more multi-programmable based resistive random access memory (RRAM) cell. A fin-type based selector is provided over the substrate in the first region. A storage element of the RRAM cell is formed over the fin-type based selector. The fin-type based selector is coupled in series with the storage element of the RRAM cell.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xuan Anh Tran, Eng Huat Toh
  • Patent number: 10651166
    Abstract: E-fuse cells and methods for protecting e-fuses are provided. An exemplary e-fuse cell includes an e-fuse having a first end coupled to a source node and a second end selectively coupled to a ground. Further, the exemplary e-fuse includes a selectively activated shunt path from the source node to the ground. Also, the exemplary e-fuse includes a device for activating the shunt path in response to an electrical overstress event.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Handoko Linewih, Chien-Hsin Lee
  • Patent number: 10643725
    Abstract: Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ping Zheng, Eng Huat Toh, Elgin Kiok Boone Quek
  • Patent number: 10643990
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an ultra-high voltage resistor and methods of manufacture. The structure includes at least one resistor coupled to a well of a doped substrate, the at least one resistor being separated vertically from the well by an isolation region with one end of the resistor being attached to an input pad and another end coupled to circuitry.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Donald R. Disney, Jongjib Kim, Wen-Cheng Lin