Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region; an emitter region above the intrinsic base region; a collector region under the intrinsic base region; and an extrinsic base region comprising metal material, and which surrounds the intrinsic base region and the emitter region.

Abstract: A semiconductor memory device is provided. The memory device includes a first electrode, a resistive layer, and a second electrode. The resistive layer is arranged over the first electrode. The second electrode is arranged over the resistive layer. The second electrode includes a lower surface and an extension extending from under the lower surface. The extension is at least partially arranged within the resistive layer.

Abstract: The embodiments herein relate to semiconductor memory devices and methods of forming the same. A semiconductor memory device is provided. The semiconductor memory device includes a memory cell having a first electrode, a second electrode, a switching layer, and a via structure. The second electrode is adjacent to a side of the first electrode and the switching layer overlays uppermost surfaces of the first and second electrodes. The via structure is over the uppermost surface of the second electrode.

Abstract: A device may include a first conductive element and an interlevel dielectric arranged over the first conductive element. The device may further include a dual damascene opening including a first end, a second end, and sidewalls extending between the first and second ends, the sidewalls extending through the interlevel dielectric. A metal-insulator-metal (MIM) stack may line the dual damascene opening. The MIM stack may include a first conductive liner lining the sidewalls and the second end of the dual damascene opening, an insulator layer lining the first conductive liner, and a second conductive liner lining the insulator layer. A first metal interconnect may be disposed in and filling the dual damascene opening lined with the MIM stack.

Abstract: A semiconductor device may include: a substrate; a protective region provided over the substrate; and a core structure enclosed by the protective region. The core structure may include a core material etchable by a chemical solution. The protective region may include a protective material resistant to etching by the chemical solution. The core structure may have a first side and a second side opposite to the first side, the first side being closer to the substrate than the second side. The core structure may be narrowest at the first side of the core structure.

Abstract: A structure includes a photodetector including alternating p-type semiconductor layers and n-type semiconductor layers in contact with each other in a stack. Each semiconductor layer includes an extension extending beyond an end of an adjacent semiconductor layer of the alternating p-type semiconductor layers and n-type semiconductor layers. The extensions provide an area for operative coupling to a contact. The extensions can be arranged in a cascading, staircase arrangement, or may extend from n-type semiconductor layers on one side of the stack and from p-type semiconductor layers on another side of the stack. The photodetector can be on a substrate in a first region, and a complementary metal-oxide semiconductor (CMOS) device may be on the substrate on a second region separated from the first region by a trench isolation. The photodetector is capable of detecting and converting near-infrared (NIR) light, e.g., having wavelengths of greater than 0.75 micrometers.

Abstract: A capacitor structure for an integrated circuit (IC) and a related method of forming are disclosed. The capacitor structure includes three electrodes. A planar bottom electrode has a first insulator layer thereover. A middle electrode includes a conductive layer over the first insulator layer and a plurality of spaced conductive pillars contacting the conductive layer. A second insulator layer extends over and between the plurality of spaced conductive pillars and contacts the conductive layer. An upper electrode extends over the second insulator layer, and hence, over and between the plurality of spaced conductive pillars. A length of the upper electrode can be controlled, in part, by the number and dimensions of the conductive pillars to increase capacitance capabilities per area.

Abstract: The present disclosure relates to sensors and, more particularly, to magnetic field sensors. More specifically, a structure includes a package with a wraparound geometry and discontinuous ends, and includes a low permeability magnetic material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a bipolar transistor device, including a base region, having a base contact region, in a first well of a first conductivity type, a collector region, having a collector contact region, in a second well of a second conductivity type, and an emitter region, having an emitter contact region, in the first well, located between the base contact region and the second well, and a reverse-doped resistance well, of the second conductivity type, located in the first well of the first conductivity type between the base contact region and the emitter contact region structured to decrease turn-on voltage of the bipolar transistor device.

Abstract: Structures for a laser-detection device including a magnetic-tunneling-junction layer stack and related methods. The structure has a magnetic-tunneling-junction layer stack including a fixed layer, a free layer, and an insulating spacer between the fixed layer and the free layer, and a power supply coupled to the magnetic-tunneling-junction layer stack. The power supply is configured to bias the magnetic-tunneling-junction layer stack to modulate an energy barrier of the magnetic-tunneling-junction layer stack for switching between a low-resistance state and a high-resistance state in response to receiving incident electromagnetic radiation of an intensity.

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure includes a first field-effect transistor on a first substrate and a second field-effect transistor on a second substrate. The first field-effect transistor includes a first gate, and the second field-effect transistor includes a second gate. The structure further includes a first interconnect structure on the first substrate and a second interconnect structure on the second substrate. The first interconnect structure includes a first metal feature connected to the first gate, and the first metal feature has a first surface. The second interconnect structure includes a second metal feature connected to the second gate, and the second metal feature has a second surface that is connected to the first surface of the first metal feature.

Abstract: A device includes a first region disposed on a substrate, a second region disposed on the first region, a third region disposed in the second region and a first terminal region disposed in the third region. The first region comprises a discontinuous layer including at least one gap portion. The at least one gap portion comprises a portion of the substrate. The first region and the second region have a first conductivity type, and the substrate, the third region and the first terminal region have a second conductivity type. The first conductivity type is different from the second conductivity type.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to improved turn-on voltage of high voltage electrostatic discharge device and methods of manufacture. The structure comprises a high voltage NPN with polysilicon material on an isolation structure located at a base region, the polysilicon material extending to at least one of a collector and emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT.

Abstract: A memory device may be provided, including a first electrode, an insulating element arranged over the first electrode, a second electrode arranged over the insulating element, a switching layer and a conductive line electrically coupled to the second electrode. Each of the first electrode, the insulating element, and the second electrode may include a first side surface and a second side surface. Centers of the first electrode, the insulating element, and the second electrode may be substantially vertically aligned. The first side surface and the second side surface of the second electrode may be substantially vertically aligned with the first side surface and the second side surface of at least one of the insulating element and the first electrode. The switching layer may be conformal to the first side surfaces and the second side surfaces of the second electrode and the insulating element.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure including a switching element arranged between a pair of conductors, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure includes a switching element arranged between a pair of conductors, in which the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure comprising a vertical silicon controlled rectifier (SCR) connecting to an anode, and comprising a buried layer of a first dopant type in electrical contact with an underlying continuous layer of a second dopant type within a substrate.

Abstract: The present disclosure generally relates to semiconductor devices for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to photodiodes such as avalanche photodiodes (APDs) and single photon avalanche diodes (SPADs).

Abstract: A device may include a substrate, and an interlevel dielectric arranged over the substrate. The interlevel dielectric may include a first interlevel dielectric layer in an interconnect level i, the first interlevel dielectric layer having a first interconnect and a second interconnect therein. A nitride block insulator may be arranged over the first interlevel dielectric layer and over the first interconnect and the second interconnect. An opening may be arranged in the nitride block insulator, the opening extending through the nitride block insulator to expose a surface of the first interconnect in the first interlevel dielectric layer. A contact plug may be arranged in the opening of the nitride block insulator. The contact plug at least lines the opening and prevents out-diffusion of conductive material from the first interconnect. A thin film of a passive component may be arranged over the nitride block insulator and over the contact plug.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a vertical silicon-controlled rectifier (SCR) connecting to an anode, and includes a buried layer of a first dopant type in electrical contact with an underlying buried layer a second dopant type split with an isolation region of the first dopant type within a substrate.

Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure includes a drift well in a semiconductor substrate, source and drain regions in the semiconductor substrate, a gate dielectric layer on the semiconductor substrate, and a buffer dielectric layer on the semiconductor substrate over the drift well. The buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge toward the first side edge. The first section has a first thickness, and the second sections have a second thickness less than the first thickness. A gate electrode includes respective portions that overlap with the buffer dielectric layer and with the gate dielectric layer.