Patents Assigned to GLOBALFOUNDRIES Singapore Pte. Ltd.
  • Patent number: 10497820
    Abstract: A method of forming a wedge-shaped fiber array and a bottom base according to a probing pad layout of a Si-Photonic device to enable optical, DC and RF mixed signal tests to be performed at the same time and the resulting device are provided. Embodiments include a bottom base; and a fiber array with sidewalls and a top surface having a first angle and a second angle, respectively, over the bottom base, wherein the fiber array is structured to expose bond pads of a Si-Photonic device during wafer level Si-Photonic testing.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: December 3, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Dandan Wang, Lei Zhu, Zhihong Mai, Jeffrey Chor-Keung Lam
  • Patent number: 10490728
    Abstract: Microelectromechanical System (MEMS) devices and related fabrication methods. A piezoelectric stack is formed on a substrate and is separated from the substrate by a dielectric layer. The piezoelectric stack is formed that includes first and second piezoelectric layers with a first electrode below the first piezoelectric layer, as well as a contact pad and a second electrode between the first and second piezoelectric layers. A first contact is formed that extends through the piezoelectric layers and contact pad to the first electrode. A second contact is formed that extends through the second piezoelectric layer to the second electrode. The contact pad prevents an interface to form between the first and second piezoelectric layers in the contact opening, thus preventing corrosion of the piezoelectric layers during contact formation process.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: November 26, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Jia Jie Xia, Minu Prabhachandran Nair, Zouhair Sbiaa, Ramachandramurthy Pradeep Yelehanka, Rakesh Kumar
  • Patent number: 10490745
    Abstract: Methods of forming planar RRAM and vertical RRAM with tip electrodes and the resulting devices are provided. Embodiments include forming a first metal oxide layer on a first dielectric layer; forming and patterning a mask layer over the first metal oxide layer; etching the first metal oxide through the mask layer to form openings for a first and second metal electrodes; removing the mask layer; forming the first and second metal electrodes in the openings; and forming a second metal oxide layer over the first and second metal electrodes, wherein the first and second metal electrodes are v-shaped in top view with tips of the first and second metal electrodes facing each other and a portion of the second metal oxide layer being formed between the tips of the first and second electrodes.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: November 26, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Jianxun Sun, Juan Boon Tan, Kwang Sing Yew, Wanbing Yi, Curtis Chun-I Hsieh, Tupei Chen
  • Patent number: 10483121
    Abstract: A low-k dielectric layer, such as SiCOH, with high and stable chemical mechanical polishing (CMP) removal rate (RR) is disclosed. The polishing rate enhancer (PRE) is disposed on the low-k dielectric layer. The PRE increases the CMP RR during CMP. Furthermore, the PRE stabilizes the increases CMP RR. This is particularly useful, for example, for memory applications in which the storage unit is formed in a low-k back-end-of-line (BEOL) dielectric layer. For example, the topography created can be quickly planarized by CMP while producing a uniform polished surface of the low-k dielectric layer due to the shortened processing time.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: November 19, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lei Wang, Chim Seng Seet, Kai Hung Alex See
  • Patent number: 10483461
    Abstract: Method of forming embedded MRAM in interconnects using a metal hard mask process and the resulting device are provided. Embodiments include forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level; forming a capping layer over the first ILD layer; forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer; forming a second metal (Mx+1) level in the second ILD layer; forming a second capping layer over the second ILD layer; and forming a third metal (Mx+2) level in a third ILD layer over the second capping layer.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: November 19, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Yi Jiang, Bharat Bhushan, Mahesh Bhatkar, Juan Boon Tan
  • Patent number: 10475495
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a first free layer that is magnetic, a second free layer that is magnetic, and an insertion layer positioned between the first and second free layers. The insertion layer is non-magnetic, and the insertion layer includes terbium.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wai Cheung Law, Taiebeh Tahmasebi, Chim Seng Seet, Kai Hung Alex See, Gerard Joseph Lim, Wen Siang Lew
  • Patent number: 10475990
    Abstract: Methods of forming a pillar contact extension within a memory device using a self-aligned planarization process rather than direct ILD CMP and the resulting devices are provided. Embodiments include forming a photoresist layer over a low-K layer formed over an ILD having a first metal layer in a memory region and in a logic region and pillar-shaped conductors formed atop of the first metal layer only in the memory region; forming a trench through the photoresist layer over each pillar-shaped conductor; extending the trench through the low-K layer to an upper surface of each pillar-shaped conductor; forming a second metal layer over the low-K layer, filling the trench entirely; and planarizing the second metal layer until the second metal layer is removed from over the logic region, a pillar contact extension formed atop of each pillar-shaped conductor.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Curtis Chun-I Hsieh, Lup San Leong, Wanbing Yi, Cing Gie Lim, Yi Jiang, Juan Boon Tan
  • Patent number: 10476480
    Abstract: A dual-mode resonator, devices employing the dual-mode resonator, and the methods of making the resonator and the devices are disclosed. Embodiments include a dual-mode resonator including a semiconductor substrate; a material on the semiconductor substrate, having a cavity formed therein; a seed layer over the cavity in a V-shape, wherein sides of the V-shape form an angle of 15 to 25 degrees with a horizontal line; a bottom electrode on the seed layer; an acoustic layer on the bottom electrode; a top electrode on the acoustic layer; and a mass loading layer on the top electrode; and a cap over the dual-mode resonator.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Humberto Campanella-Pineda, You Qian, Rakesh Kumar
  • Patent number: 10475803
    Abstract: Method for forming a memory device are disclosed. Embodiments include forming memory cells over a substrate, each memory cell includes a control gate (CG) formed over a floating gate (FG) and a select gate (SG) formed adjacent to a first side of the CG and FG, wherein a vertical oxide layer is formed between the SG and the CG and FG, forming an implant mask layer over a portion of the SG, CG and vertical oxide of each memory cell; and implanting dopants into the substrate using the implant mask to form source drain (S/D) regions between the memory cells.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Anson Heryanto, Eng Huat Toh, Yongshun Sun, Yoke Leng Lim, Siow Lee Chwa
  • Patent number: 10475891
    Abstract: Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region having a pair of non-volatile memory cells with a split gate. A split gate includes first and second gates. The first gate is an access gate and the second gate is a storage gate with a control gate over a floating gate. A common second S/D region is disposed adjacent to second gates of the first and second memory cells and first S/D regions are disposed adjacent to the first gates of the first and second memory cells. An erase gate is disposed over the common second S/D region. The erase gate is isolated by the second S/D and second gates by dielectric layers. A silicide block is disposed over the memory cell pair, covering the erase gate at least portions of the second gates of the memory cells.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Jin Qiu Liu, Fan Zhang, Lai Qiang Luo, Xin Shu Cai, Eugene Kong, Zhiqiang Teo, Fangxin Deng
  • Patent number: 10475985
    Abstract: Magnetic random access memory (MRAM) fan-out wafer level packages with package level and chip level magnetic shielding and methods of forming these magnetic shields processed at the wafer-level are disclosed. The method includes providing a MRAM wafer prepared with a plurality of MRAM dies. The MRAM wafer is processed to form a magnetic shield layer over the front side of the MRAM wafer, and the wafer is separated into a plurality of individual dies. An individual MRAM die includes front, back and lateral surfaces and the magnetic shield layer is disposed over the front surface of the MRAM die. Magnetic shield structures are provided over the individual MRAM dies. The magnetic shield structure encapsulates and surrounds back and lateral surfaces of the MRAM die. An encapsulation layer is formed to cover the individual MRAM dies which are provided with magnetic shield structures.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bharat Bhushan, Juan Boon Tan, Wanbing Yi, Pak-Chum Danny Shum
  • Patent number: 10468427
    Abstract: Devices and methods of forming a device are disclosed. A substrate is prepared with a memory region and a capacitor region. Split non-volatile memory (NVM) cell may be formed in the memory region and a capacitor may be formed in a capacitor region. The split NVM cell and the capacitor are formed with the same gate electrode and dielectric layers. The capacitor may be a poly-insulator-poly (PIP) which may include first and second capacitor control gate stacks or capacitor plates. In the case of capacitor control gate stacks, the capacitor is integrated into the device without the need of an additional mask. In the case of capacitor plates, the capacitor is integrated into the device with only one additional mask.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xinshu Cai, Shyue Seng Tan
  • Patent number: 10468457
    Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode and a base layer over the bottom electrode. The spin transfer torque magnetic random access memory structure further includes a fixed layer over the base layer. The fixed layer includes anti-parallel layers including cobalt tungsten/platinum (CoW/Pt) bilayers, cobalt molybdenum/platinum (CoMo/Pt) bilayers, or bilayers including a combination of at least two materials selected from cobalt (Co), tungsten (W), molybdenum (Mo), platinum (Pt), palladium (Pd) or iridium (Ir). Also, the spin transfer torque magnetic random access memory structure includes a magnetic tunnel junction (MTJ) element with a perpendicular orientation over the fixed layer and a top electrode over the MTJ element.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Dinggui Zeng, Kah Wee Gan, Kazutaka Yamane
  • Patent number: 10468454
    Abstract: Methods of forming a thin-film piezoelectric acoustic filter, a GaN-channel/buffer Bragg reflector, and a monolithically integrated GaN HEMT PA and CMOS over a [111] crystal orientation Si handle of a SOI wafer and resulting devices are provided. Embodiments include providing a SOI wafer including a [111] crystal orientation Si handle, a BOX layer, and a top Si layer; forming a CMOS device over the top Si layer; and forming a Bragg reflector over the [111] crystal orientation Si handle wafer, the Bragg reflector including a GaN stack with alternating layers of high/low acoustic impedance.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Humberto Campanella-Pineda, Anthony Stamper, Vibhor Jain
  • Patent number: 10468171
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a seed layer, first and second pinned layers, and a coupling layer. The seed layer includes holmium. The first pinned layer overlies the seed layer, where the first pinned layer is magnetic, and the non-magnetic coupling layer overlies the first pinned layer. The second pinned layer overlies the coupling layer, where the second pinned layer is also magnetic.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wai Cheung Law, Taiebeh Tahmasebi, Dimitri Houssameddine, Michael Nicolas Albert Tran, Chim Seng Seet, Kai Hung Alex See, Wen Siang Lew
  • Patent number: 10461247
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first, second and third regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the first and second regions. A MRAM cell which includes a MTJ element sandwiched between top and bottom electrodes is formed in the second region. The bottom electrode is in direct contact with the metal line in the first upper interconnect level of the second region. A dielectric layer which includes a second upper interconnect level with a dual damascene interconnect in the first region and a damascene interconnect in the second region is provided over the first upper dielectric layer. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the damascene interconnect in the second region is coupled to the MTJ element.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Juan Boon Tan, Yi Jiang, Wanbing Yi, Francis Yong Wee Poh, Hai Cong
  • Patent number: 10453969
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a source, a drain, and a channel defined between the source and drain. A memory cell overlies the channel, where the memory cell includes a floating gate and a control gate overlying the floating gate. A block overlies a portion of the drain referred to as a blocked drain region, where the blocked drain region is adjacent to the channel. A drain silicide overlies the drain and terminates at the blocked drain region such that the blocked drain region is between the drain silicide and the channel.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yuan Sun, Shyue Seng Tan
  • Patent number: 10453830
    Abstract: Integrated circuits, wafer level integrated III-V device and CMOS driver device packages, and methods for fabricating products with integrated III-V devices and silicon-based driver devices are provided. In an embodiment, an integrated circuit includes a semiconductor substrate and a plurality of transistors in and/or overlying the semiconductor substrate. The plurality of transistors form a gate driver circuit. The integrated circuit further includes a gate driver electrode coupled to the gate driver circuit. Also, the integrated circuit includes a III-V device electrode overlying and coupled to the gate driver electrode. The integrated circuit includes a III-V device overlying and coupled to the III-V device electrode.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventor: Donald Ray Disney
  • Patent number: 10453836
    Abstract: A method of forming a LDMOS with a self-aligned P+ implant and LVPW region at the source side and the resulting device are provided. Embodiments include forming a DNWELL in a p-sub; forming a PWHV in the DNWELL; forming an NW in the DNWELL; forming a LVPW in the PWHV; forming STI structures through the LVPW and through the DNWELL and NW, respectively; forming a gate over the PWHV; forming a first and a second P+ implant in the LVPW, an edge of the second P+ implant aligned with an edge of the gate; forming a first N+ implant in the LVPW between the first STI structure and the second P+ implant and a second N+ in the NW adjacent to the second STI structure; and forming contacts over the first and second P+ and N+ implants, respectively, and an electrical contact over the second N+ implant.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yohann Frederic Michel Solaro, Vvss Satyasuresh Choppalli, Chai Ean Gill
  • Patent number: 10446205
    Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode, a seed layer over the bottom electrode, a hard layer over the seed layer, a magnetically continuous transition layer over the hard layer, a reference layer over the magnetically continuous transition layer, a tunnel barrier layer over the reference layer, a storage layer formed over the tunnel barrier layer, and a top electrode. The reference layer, the tunnel barrier layer, and the storage layer form a magnetic tunnel junction (MTJ) element with a perpendicular orientation.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Taiebeh Tahmasebi, Dimitri Houssameddine, Michael Nicolas Albert Tran, Chenchen Jacob Wang