Abstract: Method and circuit for recording and detecting a program end signal which enable a new program to be recorded after the end of previously recorded program on a video tape by searching an end portion of the previous program.

Abstract: Methods of hyperfine patterning and manufacturing semiconductor devices. Steps in accordance with the present invention include coating a hemisphere particle layer having hills and valleys on a layer to be etched, the hemisphere particle layer having an etch selectivity higher than that of the first layer, filling the valleys of the hemisphere particle layer with a second layer having an etch selectivity higher than that of the hemisphere particle layer, and etching back the hills of the hemisphere particle layer to expose the first layer by using the second layer as a mask, and etching the first layer. By virtue of the hemisphere particle layer having alternating hills and valleys, it is possible to accomplish a hyperfine patterning of about 0.1 .mu.m. Since the mean size and the density of hills and valleys of the hemisphere layer can be controlled, the pattern size also can be controlled.

Abstract: A wide-band sample and hold circuit comprising an input buffer for inputting an analog input signal and buffering the inputted analog input signal, 1/2 frequency divider for frequency-dividing a sample and hold clock signal by two and outputting a 1/2 frequency clock signal, first switching circuit for switching in turn an output signal from said input buffer to sample and hold condensers in accordance with the 1/2 frequency clock signal, second switching circuit for switching selectivel sample and hold signals from the sample and hold condensers in accordance with said 1/2 frequency clock signal and transferring or block the selectively switched sample and hold signals in accordance with an inverted sample and hold clock signal, and an output buffer for buffering an output signal from said second switching circuit and outputting the buffered signal as an output signal of the sample and hold circuit.

Abstract: A carry transfer apparatus having a plurality of groups is provided.

Abstract: A process for formation of an LDD transistor and a structure thereof are disclosed in which the junction capacitance and the body effect can be properly reduced. In the conventional LDD transistors, the punch-through problem is serious, and the improved conventional LDD transistor also, there is a limit in increasing the channel concentration, as well as the body effect being increased. The present invention gives solutions to the above problems by arranging that the junction thicknesses of n+ source and drain become smaller than the junction thicknesses of n- regions, and that a p type pocket 6 be formed only near a gate and a p type pocket 6.

Abstract: A dynamic random access memory having an improved layout capable of having a large storage capacity with a small memory cell area as well as preventing the occurrence of short-circuiting by an increase in the process margin, and a method of arranging memory cells of the same. Each active region includes a first diffusion region, a second diffusion region in common with an adjacent memory cell and a channel forming region located between the first and second diffusion regions. First diffusion regions of adjacent active regions are located at positions symmetrical with respect to the common second diffusion region, at a predetermined angle. Each of uniformly spaced bit lines has a protrusion having a predetermined width and length and extending from its one edge in a direction that the word lines extend. At the protrusion, one second diffusion region is disposed. Uniformly spaced word lines cross bit lines. Each capacitor is positioned between two adjacent bit lines and between two adjacent word lines.

Abstract: There is disclosed a tensile strained blue-green II-VI quantum well laser. The tensile strained blue-green II-VI quantum well laser comprises of a semiconductor substrate; a buffer layer formed on the semiconductor substrate; a first ZnSe cladding layer formed on the buffer layer; a multi-quantum well layer formed on the first ZnSe cladding layer, consisting of a ZnS.sub.y Se.sub.1-y active region and a Mg.sub.z Zn.sub.1-z S.sub.w Se.sub.1-w barrier region; a current-restricting layer formed on the multi-quantum well layer; a second ZnSe cladding layer formed on the current-restricting layer; and a cap layer formed on the second ZnSe cladding layer. The inventive tensile strained blue-green II-VI quantum well laser is capable of reducing the oscillation wavelength into not more than 500 nm at room temperature and of lowering the threshold current density to as low as 1,000 A/cm.sup.2.

Abstract: A static random access memory with a double vertical channel structure capable of providing a highly integrated memory element and a method of the same. On a substrate of a first conductivity type, first and second layers of the same conductivity type are formed, in order. On respective surfaces of the three layers, impurity diffusion regions are formed, centers of which are located on a vertical line. The first layer having the second impurity diffusion region and the second layer having the third impurity diffusion region are removed at their center portions, except for their opposite side portions, thereby forming trenches. In these trenches, gate electrodes and a ground electrode are formed. Accordingly, the first impurity diffusion region and the remaining opposite side portions of second and third impurity diffusion regions become source/drain regions, while the remaining opposite side portions of first and second layers become a double vertical channel region.

Abstract: A method for forming a MLR pattern.The method comprises the steps of:forming a bottom resist film on a semiconductor substrate in which a semiconductor device is formed;forming a inter-layer on the bottom resist film;forming a top resist film on the inter-layer, wherein a first top resist film made of an inorganic material and a second top resist film made of another inorganic material and formed on the first top resist film;exposing the top resist film using a pattern mask;etching the exposed portion of the second top resist film of the top resist film;etching the first top resist film using the remained-unexposed portion of the second top resist file made of the second inorganic material as an etch mask, to form a pattern of the top resist film;etching the inter-layer and the bottom resist film using the pattern of the top resist film as an etch mask, in this order, to form a MLR pattern; andremoving the pattern of the top resist film.

Abstract: A method for fabricating a transistor having a lightly doped drain structure is disclosed.

Abstract: A method for isolating elements in a silicon semiconductor device is disclosed. The invention discloses the steps of: (1) forming a thermal silicon oxide layer on a silicon substrate, depositing a layer of polysilicon, and depositing a first silicon nitride layer thereon, (2) patterning an active region and a field region, and etching the thermal oxidation layer, the polysilicon layer and the first silicon nitride layer on the field region to forth an active region pattern, (3) depositing a second silicon nitride layer, and, thereupon, depositing a silicon oxide layer, (4) etching back the oxide layer by application of a reactive ion etch technique, forming a silicon oxide side wall on the side of the active region pattern, and etching back the second silicon nitride layer using the oxide side wall as a mask to expose the silicon substrate, (5) removing the oxide side wall, and performing a channel stop field ion implantation, and (6) performing a field oxidation process to form a field oxide layer.

Abstract: A sensor device for a mass flow controller suitable for stably sensing gas flowrate of the mass flow controller regardless of variation of peripheral temperature.

Abstract: A method for fabricating an LDD MOS transistor having an improved structure capable of simplifying the fabrication and improving characteristics of the transistor.

Abstract: A preheaterless manual transfer mold die for encapsulating semiconductor elements in a process for packaging semiconductors. The preheaterless manual transfer mold die includes a multi-plunger assembly adapted for upward and downward movement to press the resin. A tablet loader is inserted into an upper mold die in order to charge tablets into plunger bushes of the upper mold die. After charging, the loader is pulled out of the upper mold die. The upper mold die receives the tablets from the tablet loader. The tablets are pressed by the multi-plungers. A lower mold die, clamped to the upper mold die, receives the resin tablets in a gel state from the upper mold die and fills cavities of chases with the resin to mold semiconductor elements.

Abstract: A method for fabricating a thin film transistor capable of increasing an ON/OFF current ratio and decreasing a consumption of electric power.

Abstract: A DRAM having bidirectional global bit lines is defined such that local bit lines connected to corresponding memory cells and separative global bit lines connected to the local bit lines are commonly connected to local bit lines so as to read data stored in the cells or write data to the cells in a bidirectional data access manner. According to the DRAM of the present invention, the sense amplifiers, input and output lines and switching elements for column decoding, which generally are located between adjacent cell arrays, can be advantageously positioned without decreasing the characteristics of the DRAM element. In addition, the DRAM of the present invention employs an open bit line structure rather than a folded bit line structure, thereby improving a packing effect as well as a S/N (signal-to-noise) characteristic, remarkably.

Abstract: A method for fabricating an asymmetry HS-GOLD MOSFET by use of a photo etch process in place of a large tilt implantation process, capable of improving a packing density and reducing a junction capacitance of a source region, thereby improving a characteristic of a device to be finally produced. The method includes the steps of forming a gate insulating film and a gate on a p.sup.- type semiconductor substrate, implanting n type impurity ions in the semiconductor substrate so as to symmetrically form n.sup.- type source and drain regions in the semiconductor substrate, forming an insulating film over the entire exposed surface of the resulting structure, subjecting the insulating to an anisotropic etching to form spacers at respective side walls of the gate, implanting n type impurity ions in the semiconductor substrate so as to form n.sup.+ type high concentration source and drain regions respectively adjacent to the n.sup.

Abstract: A jack-type semiconductor integrated circuit package with a jack-type connector instead of conventional leads. This package comprises a semiconductor chip which is provided with a plurality of bond pads, a jack housing which is adapted to electrically connect the package to a printed circuit board (PCB) and connected to a plurality of connection pins, a resin film which electrically connects the bond pads of the semiconductor chip to the connection pins of the jack housing, bonds the jack housing to the semiconductor chip and contains a plurality of conductive wires and a sealing resin housing which seals both the semiconductor chip and the jack housing and is formed in a predetermined shape by a molding process. The present package makes the operational reliability be improved and is especially suited for providing a high density IC memory chip package.

Abstract: A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.

Abstract: A pulse width modulation apparatus having a storage circuit for temporarily storing pulse width data inputted over a data bus and then inverting it, the pulse width data determining a pulse width, a counting circuit for counting a clock signal in response to an external pulse width modulation enable signal and an external reset signal, a comparison circuit for comparing the number of logical 0 bits of the inverted pulse width data from the storage circuit with the number of logical 1 bits of count data from the counting circuit and outputting a high signal when the number of the logical 0 bits of the inverted pulse width data is greater than or equal to the number of the logical 1 bits of the count data and a low signal when the number of the logical 0 bits of the inverted pulse width data is smaller than the number of the logical 1 bits of the count data, and an output circuit for latching an output signal from the comparison circuit to output a pulse width modulation signal.