Abstract: An EEPROM cell and a method for fabricating the same are disclosed.The EEPROM cell fabricated by the method comprises of: a first active region with a second conductive low density impurity formed in a first conductive semiconductor substrate; a second active region with a second conductive high density impurity formed in one side of said first active region; a third active region with the second conductive high density impurity formed in the other side of said first active region; a fourth active region with a first conductive high density impurity formed so as to surround said third active region; a floating gate atop a first insulating layer overlying said first active region; and a control gate atop a second insulating layer overlying said floating gate.The EEPROM cell is improved in an operational characteristic such as an erasing speed and a programming speed. The EEPROM cell is fabricated in such very small size to be integrated in a high integration degree.

Abstract: A semiconductor package having lead bars provided with upper and lower surfaces outwardly exposed, thereby enabling a stacked mounting, a memory extension and a reduction in mounting area.The semiconductor package is manufactured by attaching a plurality of lead bars arranged in two rows in a facing manner to an upper surface of an adhesive tape, each of the lead bars having a first step and a second step positioned at a higher level than the first step, attaching a semiconductor chip to the first steps of the lead bars by an insulating adhesive, wire-bonding bond pads of the semiconductor chip with the second steps of the lead bars by metal wires, respectively, molding the lead bars, the semiconductor chip and the metal wires together by a molding compound under a condition that upper and lower surfaces of the lead bars are exposed outwardly of the molding compound, and removing the adhesive tape after the molding step.

Abstract: A magnetic pencil for moving semiconductor devices is disclosed, which includes a tubular housing provided with two pin holes; a hollow push rod inserted into the housing, and having guide slots at positions corresponding to the pin holes of the housing, with its upper end being closed; an insertion rod inserted into the hollow push rod, with a magnet attached on the lower tip thereof, and with screw holes provided at positions corresponding to the guide slots; and a spring fitted between the upper tip of the insertion rod and the closed upper end of the push rod. In the assembled state, guide pins are provided between the holes of the housing and the screw holes of the insertion rod through said guide slots, respectively. When the magnetic pencil is positioned uprightly by gripping with the fingers of an operator, a semiconductor device is attached to the magnet slightly projected from the lower tip of the pencil.

Abstract: An isolation structure of a semiconductor device including a channel stop diffusion region selectively formed on a portion of a single crystalline silicon substrate disposed beneath an edge of a field oxide film formed on the substrate, thereby capable of selectively increasing, irrespective of a pattern size of the field region, a channel ion concentration at an edge of a field region where the field region is connected to an active region and which region is a weak area serving to decrease a channel stop ion concentration at an interface between the field oxide film and the silicon substrate and to decrease a threshold voltage of a field transistor due to a small thickness thereof and thereby locally increasing the threshold voltage. By the local increase in threshold voltage, it is possible to prevent a degradation in insulating characteristic of the field transistor with a small pattern size.

Abstract: A circuit for a clamping an /RAS signal in a DRAM. The bit line pre-charge generator is activated after the set-up of the VBB voltage, so that /RAS signals may be supplied to the chip after the bit line pre-charge voltage (VBLP) has reached the desired level, thereby preventing malfunction of the sense amplifiers.

Abstract: A carbon brush for discharging static electricity for protecting semiconductor devices from damage by the discharge of static electricity from the semiconductor devices. A plurality of carbon wires are attached to a brush securing bar in a suspending manner. Static electricity accumulated on semiconductor devices during various operations may be discharged through the brush securing bar to ground potential by coming into contact with the carbon wires.

Abstract: In the method of present invention, an LDD MOSFET is formed without using a side wall spacer as an ion implantation inhibiting layer.

Abstract: A vertical synchronous signal separation circuit is disclosed wherein the circuit includes a vertical synchronous pulse removal circuit for delaying original horizontal and vertical synchronous signals separated from a composite video signal by a predetermined time period in response to a reference clock signal and logically combining the original horizontal and vertical synchronous signals with the delayed horizontal and vertical synchronous signals to remove vertical synchronous pulses therefrom, a clock generator for logically combining an output signal from the vertical synchronous pulse removal circuit with the reference clock signal to generate a clock signal, an edge detector for detecting edges of the output signal from the vertical synchronous pulse removal circuit and outputting the detected edges as a reset signal, and a vertical synchronous signal extractor for extracting a stable vertical synchronous signal from the original horizontal and vertical synchronous signals in response to the clock sig

Abstract: A method for fabricating a thin film transistor including the steps of forming a gate electrode on a substrate; successively depositing a gate insulation layer and a semiconductor layer on the substrate; forming sidewall from semiconductor layer on both said surfaces of the gate electrode by an anisotropic dry etching process; and implanting ions into the semiconductor sidewall. The grain boundaries in the source and drain junctions but not parallel to the channel. prevent leakage current. Thus, the on-to-off current ratio is improved and the device can be designed with a reduced cell size having no off-set margins.

Abstract: A method for fabricating a phase shifting mask suitable for positive photoresist process. The method includes the steps of: (a) forming a plurality of opaque layer patterns (44) in an array at a fixed interval from each other in their width direction on a substrate (41); (b) coating an interlayer (45) on and covering the opaque layer patterns; (c) forming interlayer patterns (45) on the substrate at both longitudinal sides of each opaque layer pattern by etching the interlayer; (d) forming a plurality of insulation films (46) on the substrate between adjacent pairs of the opaque layer patterns on which the interlayer patterns are formed; (e) removing the remaining interlayer under each of the insulation films; and (f) forming a phase shifter (47) having a ninety degree area (47-2) in a region where the interlayer has been removed and a one hundred and eighty degree area (47-1) in the remainder of the region by heating the insulation film.

Abstract: A voltage generator for use in a semiconductor memory device suitable for use as a backbias voltage generator, as an internal high voltage generator, or as an internal power voltage generator. The present invention includes: a rectifier for producing a dc voltage power by rectifying clock signals; an oscillator including an odd number of invertors connected in series, and with the output of the last invertor fed back to the first invertor so as to oscillate clock pulses; and one or more bypass circuit connected so as for the output of the first invertor to bypass one or more intermediate invertors, and connected and disconnected by a control switch.

Abstract: A word-line driver of a semiconductor memory device having an address buffer for receiving a row address and a word-line decoder for converting an output signal of the address buffer into a word-line decoding signal is disclosed.

Abstract: A trench capacitor memory cell having a semiconductor substrate, an active region having a transistor on a portion of the semiconductor substrate, a field region formed by removing portion of the semiconductor substrate except for portions of the active region to a certain depth below the surface of the semiconductor substrate, a capacitor trench region formed in contact with a part of the active region and within the field region, and a polysilicon plug formed within the field region except for the trench region, and insulated by being surrounded by an insulating layer.

Abstract: A semiconductor memory device including a plurality of memory cells arranged in a matrix manner, each of the memory cells including a transfer transistor constituted by a gate electrode, a gate insulating film, a source region and a drain region, and a charge storage capacitor constituted by a storage node, a dielectric film and a plate electrode, the storage node of the charge storage capacitor including a cylindrical lower electrode formed above the transfer transistor via an insulating layer formed on the transfer transistor and connected to one of the source region and the drain region of the transfer transistor, and a cover type upper electrode formed on the lower electrode and connected with the lower electrode.

Abstract: A bus interfacing circuit for permitting a unilateral read/write first-in first-out memory to perform first-in first-out functions without data bumping when operated in bilateral data buses is disclosed.

Abstract: A method of fabricating a nonvolatile memory device including the steps of depositing a first oxide film by chemical vapor deposition over a semiconductor substrate of a first conductivity type; applying a photo etching process to the first oxide film so as to expose a portion of the semiconductor substrate; forming a gate oxide film on the exposed portion of the semiconductor substrate; coating in sequence a first polysilicon film, an insulating film, and a second polysilicon film entirely over the resultant structure; applying an etchback process to the first polysilicon film, the insulating film, and the second polysilicon film so as to form an EEPROM structure, which includes a floating gate at a sidewall of the first oxide film, the insulating film being used as an interlayer insulating film, and a control gate, the floating gate having two regions integrally formed with one region lying flat over the gate oxide film in a first direction and the other region extending from an end portion of the first reg

Abstract: A method for making semiconductor thin film transistors (TFTs) having a bottom gate such that the gate electrode is formed of a polysilicon layer with a rugged surface, thereby providing a TFT which has a high on/off current ratio. According to the present invention, a thin film transistor may have a substrate; a gate electrode having a rugged surface formed on the substrate; a gate insulating layer formed on the gate electrode and the substrate; a semiconductor layer formed over the gate insulation layer; impurity regions formed at opposite sides of the gate electrode in the semiconductor layer. A method for making a thin film transistor according to present invention may include the steps of: forming a gate electrode having a rugged surface on a substrate; forming an insulating layer and a semiconductor layer on the substrate and the gate electrode; forming impurity regions at opposite sides of the gate electrode in the semiconductor layer.

Abstract: A process for formation of an isolating layer for a semiconductor device is disclosed. During formation of a field isolating layer, a pad oxide layer is formed which is intended to buffer the difference of the thermal expansion rates between the silicon substrate and a nitride layer. First and second side wall spacers are formed, so that the flow of the oxidant into the buffering pad oxide layer should be inhibited, and that the damage-causing shear stress should be reduced. Thus the structural defect having the shape of the bird's beak is prevented, thereby securing a high density element region. Further, during the formation of a monocrystalline silicon, the growth thickness may be optimized, so that the resulting semiconductor device should be flattened, thereby simplifying the process.

Abstract: A dynamic random access memory having an improved layout capable of having a large storage capacity with a small memory cell area as well as preventing the occurrence of short-circuiting by an increase in the process margin, and a method of arranging memory cells of the same. Each active region includes a first diffusion region, a second diffusion region in common with an adjacent memory cell and a channel forming region located between the first and second diffusion regions. First diffusion regions of adjacent active regions are located at positions symmetrical with respect to the common second diffusion region, at a predetermined angle. Each of uniformly spaced bit lines has a protrusion having a predetermined width and length and extending from its one edge in a direction that the word lines extend. At the protrusion, one second diffusion region is disposed. Uniformly spaced word lines cross bit lines. Each capacitor is positioned between two adjacent bit lines and between two adjacent word lines.

Abstract: This invention relates to a method for fabrication of masks suitable for improving semiconductor wafers in resolution, which comprises processes for depositing a phases shifting layer and an opaque layer on a transparent substrate, defining an opaque area and a transparent area and removing the opaque layer from the transparent area selectively, forming side wall on the sides of the opaque layer, and removing the exposed phase shifting layer selectively using the side walls and the opaque layer as a mask.