Abstract: A metallic mold for molding semiconductor package including a pair of cavity blocks capable of molding two types of semi conductor packages in order to reduce manufacturing cost. The metallic mold includes an upper cavity block to be inserted in its normal state and its turned over state in an upper chase block mounted on a lower surface of a top mold base of an upper mold die which is formed at its upper surface with one type of cavities and at its lower surface with another type of cavities, and a lower cavity block to be inserted in its normal state and its turned over state in a lower chase bock mounted on a bottom mold base of a lower mold base which is formed at its upper surface with cavities mating with the another type of cavities of the upper cavity block and at its lower surface with cavities mating with the one type of cavities of the upper cavity block.

Abstract: A method for manufacturing a silicon semiconductor device with a high contamination sensitivity to heavy metals, such as Si-CCD solid state image sensors, wherein a gettering site is formed in an element isolation region present near an element region or the like, a non-depleted n.sup.+ or p.sup.+ region, a region to be removed or isolated from the surface of a semiconductor substrate in a subsequent process. This method makes it possible to form semiconductor devices while reducing the contamination of silicon substrate surfaces by heavy metals. The method also realizes the manufacture of silicon semiconductor devices exhibiting a stable device characteristic and having reduced defects.

Abstract: For enabling burn-in test in a memory device such that a test mode timing signal and detected voltage level of an external power supply are combined in order to maintain compatibility with conventional timing signals, and for preventing the burn-in test circuit from dissipating power in a standby state, there is provided a sense control circuit for producing a short duration enable pulse in response to an input level of timing signals such as WCBR, CBR, or ROR, and a voltage sensor for sensing the input voltage level of the external power supply voltage during the short duration pulse. Also, the circuit includes a burn-in sensor which generates a signal output which determines set or reset of the burn-in test mode in response to the timing signals and the detected level of the voltage sensor. Since the voltage sensor is operated only when the short duration pulse is applied, the power consumption in the voltage sensor is negligible even during the sensing operation of the external supply voltage.

Abstract: A method for forming a bump on a semiconductor device takes advantage of the solderability difference of the solder paste applied to a solder pad in order to form a bump, so that it does not require an etching process. In addition, a pre-test of the semiconductor device can be carried out in a state that the solder pad is united with a BLM layer, so as to prove out semiconductor devices of good quality in advance of finishing the formation of the bump and the semiconductor devices of good quality can be applied with a subsequent process.

Abstract: A photodiode capable of obtaining a sufficient photo current/dark ratio at both a forward bias state and a reverse bias state. The photodiode includes a glass substrate, an aluminum film formed as a lower electrode over the glass substrate, an alumina film formed as a Schottky barrier over the aluminum film, a hydrogenated amorphous silicon film formed as a photo conduction layer over a portion of the alumina film, and a transparent conduction film formed as an upper electrode over the hydrogenated amorphous silicon film.

Abstract: A method for fabricating a semiconductor memory, including the steps of: forming transistors on a semiconductor substrate (100); forming a first insulation film (23, 24, 25) on the semiconductor substrate; forming contact holes by selectively etching the first insulation film; forming successively a first conductive layer (26), an etch preventing film (27), and a first temporary film (28) on the substrate and the contact holes; etching the first temporary film and the etch preventing film to selectively expose the first conduction layer; forming a second temporary film (30) on the first temporary film and the first conductive layer; etching the second temporary film to form sidewall spacers of the second temporary film at sidewalls of the first temporary film; patterning the first conduction film using the first temporary film and the sidewall spacers as masks; forming a second insulation film (31) on the first conductive layer, the sidewall spacers and the first temporary film; etching the second insulation

Abstract: A method of fabricating a nonvolatile semiconductor memory device so as to improve interface properties between a tunneling oxide layer and a floating gate of the nonvolatile semiconductor memory device is disclosed, wherein the method comprises the steps of forming a tunneling oxide layer on a substrate, forming a floating gate consisting of a plurality of thin silicon layers which are formed through the repeated cyclical process under the low temperature of around 550 degrees C., forming an interposed insulating layer over a whole surface of the floating gate by a selective etching process of the silicon layers; and forming a control gate over a whole surface of the interposed insulating layer.

Abstract: A CCD type solid-state image sensor a n type silicon substrate, a first p type well formed over the substrate, photodiode regions deeply and widely formed in the first well, second p type wells formed in the first well, each of the second well being overlapped with each corresponding photodiode region and each photodiode region preceding to the corresponding photodiode region, n type VCCD channel regions respectively formed in the second wells, p type transfer gate channel regions each formed in each one of the second p type wells between each photodiode region and each corresponding VCCD channel region, p type channel stop regions respectively formed in the second wells, each of the channel stop regions being adapted to isolate each corresponding VCCD channel region from each corresponding preceding photodiode region, p type impurity regions respectively formed beneath surfaces of the photodiode regions, a thin insulating film formed over the entire exposed surface of the resulting structure, transfer gates

Abstract: A plastic semiconductor package and a method for producing the same. The package comprises a plurality of chip signal transmitting leads protruded from a semiconductor chip and functioning as electrical passage, a plurality of polyimide tapes each attached to the corresponding lead and having the same width as that of the lead, a plurality of insulating double-sided tapes each attached to a side of an upper surface of the corresponding lead for attaching the lead to the semiconductor chip, a plurality of conductive bumps each disposed to the other side of the upper surface of the corresponding lead for electrically connecting the lead to the semiconductor chip, and mold resin enveloping a predetermined area including the semiconductor chip and the leads. Since the package does not have metal wire, it is possible to reduce deterioration of a package due to wire-bonding, since the method of the invention eliminates a trimming/forming step to simplify its process.

Abstract: A method of manufacturing a capacitor in a semiconductor device such as a semiconductor memory is disclosed in which a tantalum layer is oxidized to form a tantalum oxide layer. A preferred embodiment of the disclosed method includes the steps of depositing doped polysilicon on a semiconductor substrate to form a node electrode, oxidizing the polysilicon node electrode to form a silicon oxide layer, depositing tantalum by way of a sputtering process, performing an annealing and oxidation process to form tantalum oxide and depositing polysilicon to form a plate electrode. According to the present invention, TaCl.sub.5 is not used as a solid source, and contamination can be reduced.

Abstract: A back-bias voltage generating circuit of a semiconductor device having a driving signal generating portion for receiving oscillating signals from an oscillator such as a ring oscillator and generating alternating high and low driving signals, a first pumping portion for charging the input driving signal at one electrode of a pumping capacitor so as to produce a voltage at the other electrode of the pumping capacitor lower than a back-bias voltage, a second pumping portion for charging another input driving signal at one electrode of a second pumping capacitor so as to produce a voltage at the other electrode of the second pumping capacitor lower than a back-bias voltage, a first switching portion being turned on by a voltage higher than a back-bias voltage and connecting the other electrode of the pumping capacitor to a back-bias voltage terminal when the voltage of this electrode is below the back-bias voltage, and a second switching portion being turned on by a voltage higher than a back-bias voltage and c

Abstract: A charge coupled device including a first electrode consisting of a first region and a second region having lower resistance than the first region, and a second electrode consisting of a first region and a second region having lower resistance than this first region. The first region of the first electrode is adjacent to the first region of the second region at an interval of an insulating film. Capable of utilizing the force of electrical field, the device is superior in charge transfer efficiency as well as charge transfer velocity. It also has the capability to improve the performances of high picture quality solid state image sensing devices and time delay devices, which both necessitate a charge coupled device and operate at high frequencies. Additionally, a solid state image sensing device employing this device is not degraded in a dark state by generating a few pulse charges.

Abstract: A DRAM cell and a method for fabricating the same capable of obtaining a large capacitance for achieving a high integration and yet maintaining superior characteristics of elements. A capacitor structure is provided, which includes a common storage node formed at the inner wall of a trench, and two plate electrodes connected to each other in parallel, that is, a substrate and a polysilicon layer formed over the storage node via a second dielectric film and connected to the substrate in parallel. With such a capacitor structure, the capacitance per unit capacitor area can be maximized. A source, a drain and a gate channel of each transistor and a capacitor storage node are formed by a single layer. With this structure, a minimum information transmitting path is obtained, thereby enabling the overall structure and the fabrication therefor to be simplified. Furthermore, the present invention makes it easy to form an active region where elements are formed, without using an element isolation process.

Abstract: A data output buffer, which includes a data output driver which in turn includes a pull-up circuit (14) operating in response to a first signal and a pull-down circuit (I10) operating in response to a second signal, and a control circuit for sensing a current flowing into the pull-down circuit via a feed-back and controlling the slope of the second signal in accordance with the sensed current. The control circuit includes a sensing circuit (I13) for sensing current flowing into the pull-down circuit upon driving data, and the magnitude of noises generated at the actual ground line (GND.sub.1 +GND.sub.2) due to the current, a voltage adjustment circuit (I14) which operates in response to the output signal of the sensing circuit and thereby adjusts the gate voltage of the pull-down circuit. Thereby, the noises generated in the chip are repressed without affecting the operational speed of the chip.

Abstract: An edge enhancement phase shifting mask having a recessed opaque layer which optimally exhibits the phase shifting effect at edge portion is disclosed, wherein the mask comprises a transparent substrate having at least one or more trenches spaced apart from each other by a predetermined distance, an opaque layer filling some portion of the trench, and a phase shifting layer formed on the substrate area between the trenches.

Abstract: A 3-state buffer circuit applicable for a CMOS output drive circuit is disclosed. The output circuit provides reduced ground noise and delay time of an output signal by decreasing a counter-electromotive force generated upon turning ON of the output transistor. The circuit includes a subsidiary drive circuit for applying a voltage less than the power source Vcc to a gate of an NMOS transistor connected on the ground side of the drive circuit so that generation of the counter-electromotive force is minimized.

Abstract: A Vbb generator having several distributed Vbb generators, which are located respectively adjacent to memory array blocks is disclosed. The distributed Vbb generator is activated during the time when a memory block located adjacent the Vbb generator is accessed for write/read operations. The back bias voltage generator circuit has a first Vbb generator and a second Vbb generator for supplying a back bias voltage to the substrate. The second Vbb generator comprises an oscillator for generating a clock pulse and a plurality of distributed Vbb generators.

Abstract: A thin film transistor and a method which forms a channel region (c), a lightly doped drain region (LDD) region and, optionally, an offset region (o), in a portion of a semiconductor layer which is adjacent a sidewall of the gate electrode without the use of photo masks, thereby increasing the permissible degree of miniaturization and improving production yield.

Abstract: A memory system for processing digital video signals.The memory system comprise a RBA control means for controlling a RBA using signals applied from the outside, an address generation means for generating an address using an initial address in accordance with the control of the RBA control means, a memory cell array for storing data in accordance with the control of the RBA control means and the address generation means, a transmission control means for controlling the transmission of data from the memory cell array in accordance with the control of the RBA control means and the address generation means and an input and output means for prosecuting the input and output of data in accordance with the control of the RBA control means and the transmission control means.

Abstract: A resin molded semiconductor package of which the semiconductor chip is bonded to leads instead of a paddle. This package comprises a semiconductor chip and a lead frame comprising a plurality of board connection leads and a plurality of chip connection leads. The board connection leads are connected to a circuit board and support the semiconductor chip bonded to their surfaces. The chip connection leads extend from individual board connection leads and are electrically connected to the semiconductor chip through a plurality of metal wires. A pair of chip bonding materials bond the semiconductor chip to the surfaces of the board connection leads. A predetermined volume of the package, including the semiconductor chip and the board connection leads and the chip connection leads, is hermetically sealed by a mold resin to form a package body in which the lower surfaces of the board connection leads are exposed to the outside of the lower surface of the package body.