Abstract: A reference voltage generator includes a current mirror circuit connected to a power supply voltage and having a plurality of transistors which are coupled in parallel to the power supply voltage, a reference current circuit connected between the current mirror circuit and a ground for generating a reference current in accordance with an differential operation, a feedback circuit for applying the reference current to the current mirror circuit, and a constant voltage circuit having an operational amplifier whose input terminal is connected to the current mirror circuit for generating the reference voltage.

Abstract: A self refresh control circuit for a memory cell array including a plurality of address buffers for inputting addresses of the memory cell array and a plurality of decoders for decoding the addresses from the address buffers.

Abstract: A frequency multiplier circuit comprising a first delay circuit for delaying sequentially a reference clock signal, a frequency doubler for delaying the reference clock signal and combining logically the delayed reference clock signal and the reference clock signal, a second delay circuit for delaying sequentially an output signal from the frequency doubler, a signal detector for logically combining the output signal from the frequency doubler and a plurality of output signals from the second delay circuit to detect a desired duty factor of signal, a decoder for decoding a plurality of output signals from the first delay circuit and a plurality of output signals from the signal detector to output a signal delayed by n times half a period of the reference clock signal, and a frequency generator for logically combining an output signal from the decoder and the reference clock signal to generate a multiple frequency of that of the reference clock signal.

Abstract: A process for formation of an MOS semiconductor device having an LDD structure is disclosed, which may include the steps of: forming an active region and an isolation region on a semiconductor substrate; forming a first insulating layer on the surface of the substrate; forming a gate electrode on the first insulating layer in the active region; foxing a layer of a heat sensitive fluid material on the gate electrode; carrying out a first ion implantation into the substrate; carrying out a first heat treatment on the heat sensitive layer; carrying out a second ion implantation into the substrate; removing the residual fluid material; forming a second insulating layer on the whole surface of the wafer; and carrying out a second heat treatment on the wafer.

Abstract: A degaussing circuit comprising a rectifying circuit for rectifying an AC voltage inputted therein into a DC voltage, a capacitor for smoothing the DC voltage from the rectifying circuit, a RC charging circuit for charging with the DC voltage smoothed by the capacitor, a positive temperature coefficient resistor having a resistance which is increased with an increase in a temperature due to an AC current flowing therethrough upon power supply, a degaussing coil for removing a magnetic field in response to the AC current flowing through the positive temperature coefficient resistor thereto, a relay for controlling the flow of the AC current through the positive temperature coefficient resistor to the degaussing coil, and a relay driving circuit for controlling an ON/OFF state of the relay in response to the voltage charged on the RC charging circuit.

Abstract: A horizontal charge coupled device (HCCD) is provided with a multiple reset gate in order to establish a more stable, less noisy voltage in an output node floating diffusion. Charges are transferred from an input of the HCCD to the floating diffusion by multiple, overlapping gate structures. Signal charges are detected or read out from the floating diffusion through an amplifier/inverter circuit. Periodically, the voltage of the floating diffusion is established to a reference level by application of a reset signal to a multiple reset gate structure, which results in charges in the floating diffusion being transferred to a reset drain. Noise induced by the reset operation is lessened on average due to the multiple reset gate structure.

Abstract: An output buffer is disclosed. In the prior art, when an output buffer swings to a supply voltage Vcc and a ground voltage Vss, the current drops rapidly at the supply voltage or the ground voltage, thereby generating bouncing of the supply voltage Vcc or bouncing of the ground voltage Vss. For eliminating this phenomenon, a capacitor is provided connected to an output node of the inventive output buffer to reduce the amount of the current flowing to the supply voltage terminal and the ground voltage terminal at the time point at which an output level is changed. Therefore, voltage drop and the bouncing of the supply voltage and the ground voltage is reduced by applying a precharge voltage which is precharged in the capacitor to the output node.

Abstract: The present invention provides a method of forming an insulating layer of a semiconductor device, in which an oxide layer having an optimum nitrogen concentration and also a sufficient thickness may be grown by independently regulating the flow rate of NO and O.sub.2 gas and supplying the NO and O.sub.2 gas to a reaction chamber. This method is such that the NO and O.sub.2 gas is supplied to the chamber by regulating the NO and O.sub.2 gas, while maintaining the inside of the chamber at a temperature of about 750.degree. C. to 1050.degree. C. for a predetermined time, wherein nitrogen is included in a Si/SiO.sub.2 interface.

Abstract: A bit line structure is disclosed.

Abstract: A method for driving bit line selecting signals is disclosed, in which the DRAM cell includes a plurality of memory cell arrays, sense amplifiers, bit lines, bit line equalizer sections, bit line selecting sections, data input/output sections, and bit line selection signal generating sections.

Abstract: There is provided a method for the fabrication of electroluminescence device, comprising the steps of: forming a lower electrode with a predetermined pattern on a substrate: forming a first insulation layer on the lower electrode atop the substrate, in a state of grounding the lower electrode; forming a luminescent layer on the first insulation layer; forming a second insulation film on the luminescent layer; and forming an upper electrode with a predetermined on the second insulation layer. For formation of the first insulation layer, a ferroelectric material is deposited by a sputtering process employing a sputtering apparatus consisting broadly of a vacuum chamber and an external limiter. The transparent lower electrode is electrically connected with the external limiter and grounded through it.

Abstract: An apparatus for detecting data input/output states of a plurality of FIFO memories, comprising a control signal generator for logically combining a load clock signal, a read clock signal, a write clock signal and a reset signal to generate a clock signal and a mode signal, a clock counting circuit for performing a counting operation for the read clock signal and the write clock signal in response to the clock signal and the mode signal from the control signal generator to generate a count signal, a fullness level value storage unit for storing a plurality of fullness level values, a multiplexer for selecting one of the fullness level values from the fullness level value storage unit in response to a select signal, a signal comparator for comparing an output signal from the multiplexer with the count signal from the clock counting circuit to discriminate whether it is the same as the count signal, a demultiplexer for generating a plurality of status signals in response to an output signal from the signal comp

Abstract: The present invention discloses a semiconductor memory device. The device comprises memory cells for storing data, bit line pairs connected to the memory cells and for transmitting the data, data line pairs for transmitting the data to the bit line pairs, column select transistors for controlling transmission of the data between the bit line pairs and the data line pairs, precharging transistors for precharging the data line pairs, an address state transition detecting means for generating an address state transition detection pulse by detecting state transition of an address signal, a data state transition detection means for generating a data state transition detection pulse by detecting state of the data, a control circuit for enabling the precharging transistors in response to the address state transition detection pulse, the data state transition detection pulse, and a write enable signal, thereby protecting an entry of invalid data by ensuring enough write recovery time and data hold time.

Abstract: A non-overlap signal generation circuit for a semiconductor memory device which generates two non-overlapped output signals of complementary logic levels with respect to one input signal. The circuit comprises first and second data paths. The first data path includes a first transistor for transiting a first output node from logic "0" to logic "1" when the input signal is transited from logic "0" to logic "1", whereas from logic "1" to logic "0" when the input signal is transited from logic "1" to logic "0", a first inverter for inverting the input signal, and a second transistor for transiting the first output node from logic "1" to logic "0" in response to an output signal from the first inverter.

Abstract: A solid state image sensor including (a) a plurality of photodiodes arranged such that the photodiodes in odd number columns and the photodiodes in even number columns straddle each other, for generating image signal charges by converting light signals into electrical signals, (b) vertical charge coupled devices each formed between the photodiode columns for vertically transmitting the image signal charges generated in each of the photodiodes, and (c) a plurality of microlenses each arranged matched with each of the plurality of photodiodes over each of the photodiodes. Each of the photodiodes is shaped like a peanut shell having a narrower middle part. The photodiodes shape is thereby matched to the focusing shape of each matching microlens, optimizing the cell layout efficiency.

Abstract: An on-screen display circuit of the interlaced scanning type comprising a vertical counter for counting a horizontal synchronous signal inputted thereto and outputting the counted values as higher-order bits of a vertical address, a 1-bit counter for counting a vertical synchronous signal inputted thereto by one bit and outputting the counted value as a least significant bit of the vertical address, a vertical decoder for decoding output signals from the vertical counter and the 1-bit counter to designate a decoded vertical address, a character decoder for decoding a character address inputted thereto to designate a decoded horizontal address, and a font read only memory for outputting font data in its location corresponding to the decoded vertical address from the vertical decoder and the decoded horizontal address from the character decoder.

Abstract: A memory redundancy circuit using FLOTOX transistors instead of conventional link fuses and thus capable of redundancy programming even after the packaging of the chip. The redundancy circuit is capable of generating spare signals in order to use spare memory cells for particular addresses. The circuit includes: a reference line having a certain voltage level for generating spare signals; a reference voltage supplying circuit for supplying the required voltage to the reference line; two or more FLOTOX transistors connected to the reference line; and high voltage driving circuits provided for the FLOTOX transistors, and connected to address lines in such a manner as to supply the required voltage to the gates of the FLOTOX transistors for programming.

Abstract: An improved transfer molding apparatus is provided for molding a preheated resin under pressure to thereby encapsulate a small element, such as a semiconductor device or package. In one aspect of the invention, the improvement consists of providing a shortened pot into which a piston is forcibly pressed to generate a flow of preheated resin in the encapsulating process, the improvement comprising the replacement of a single-element top drive plate, as found in a conventional apparatus, by a two-piece top drive plate which enables a shortening of the pot and corresponding reduction in the amount of air that would otherwise be trapped between the plunger and the resin during the process. The elimination of this air significantly reduces foaming, porosity, voids, and other defects in the cured resin which finally surrounds the electrical elements encapsulated thereby.

Abstract: A capacitor of a semiconductor memory cell having a maximized capacitance and a process for formation thereof are disclosed. The process is characterized in that a projected portion or a depressed portion is formed. Sets of polysilicon layers and silicon oxide layers are stacked over the projected or depressed portion. The sets of stacked layers are etched back, so that the layers having a slower etch rate remain in the form of multi-layer rims. An underlying silicon oxide layer is etched using the multi-layer rims as a mask to form a multi-layer cylinder. Then a polysilicon layer is deposited and etched back deeper than the thickness of the polysilicon layer. The silicon oxide layer is subjected to a wet etch to form a multi-layer cylindrical storage electrode. Then a dielectric layer and cell plate are formed on the storage electrode.

Abstract: The capacitor area is increased with a cylinder-shaped first storage electrode overlapped with a second electrode in an area which covers two adjacent cells. Included in a semiconductor device using the invention may be: a semiconductor substrate; a word line on the substrate; impurity regions at opposite sides of the word line in the substrate; a first contact hole on an odd impurity region; a first storage electrode connected to the first contact hole, which is overlapped with an adjacent even cell; a first sidewall storage electrode at opposite sides of the fist storage electrode; a second contact hole on the even impurity region, the second contact hole having a insulated sidewall; a second storage electrode connected to the second contact hole, which is overlapped with an adjacent odd cell; a second sidewall storage electrode at opposite sides of the second storage electrode.