Abstract: A non-volatile static random access memory cell and includes a bistable regenerative circuit coupled to first and second transistors and to first and second non-volatile memory cells. Methods of use include directly transferring a complementary data bit between the non-volatile memory cell and the bistable regenerative circuit. Alternatively, complementary data from the bistable regenerative circuit may be regenerated by a sense amplifier and a second bistable regenerative circuit before being transferred to non-volatile memory cells in a column of memory cells. The bistable regenerative circuit may be reset to ground potential. Applications using the non-volatile SRAM cell with direct read out from the bistable regenerative circuit include a non-volatile flip-flop or non-volatile multiplexer.

Abstract: A method and system for providing a magnetic element and a magnetic memory utilizing the magnetic element are described. The magnetic element is used in a magnetic device that includes a contact electrically coupled to the magnetic element. The method and system include providing pinned, nonmagnetic spacer, and free layers. The free layer has an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy corresponding to a perpendicular anisotropy energy that is less than the out-of-plane demagnetization energy. The nonmagnetic spacer layer is between the pinned and free layers. The method and system also include providing a perpendicular capping layer adjoining the free layer and the contact. The perpendicular capping layer induces at least part of the perpendicular magnetic anisotropy in the free layer. The magnetic element is configured to allow the free layer to be switched between magnetic states when a write current is passed through the magnetic element.

Abstract: A method for determining switching characteristics in electronic devices is disclosed. The method includes applying a ramped series of electrical pulses, identifying a candidate switching pulse, grouping the measured parameter values for the remaining electrical pulses, extrapolating an expected parameter value for the candidate switching pulse for each group, and comparing the expected parameter value for each group to the parameter value for the candidate switching pulse. The method also includes applying a ramped series of electrical pulses, identifying a candidate switching pulse, and clustering the remaining measured parameter values.

Abstract: Circuit includes, in part, random access memory cells, column decoders, row decoders, and write driver circuit. Driver circuit is responsive to data and control signals. Writing data includes multiple write phases, each phase driving predetermined current through selected cell by driver setting predetermined voltages to first and second lines. Voltages are in sets such that sequential voltages of each set correspond to respective phase. During writing of first data to selected cell, driver circuit causes first signal line to be at second voltage set and second signal line to be at first voltage set. Second voltage set is greater than first voltage set. During writing of second data to selected cell, driver cause first signal line to be at third voltage set and second signal line to be at fourth voltage set. Third voltage set is smaller than the fourth voltage set.

Abstract: A method and system for providing a magnetic junction residing on a substrate and usable in a magnetic device are described. The magnetic junction includes a first pinned layer, a first nonmagnetic spacer layer having a first thickness, a free layer, a second nonmagnetic spacer layer having a second thickness greater than the first thickness, and a second pinned layer. The first nonmagnetic spacer layer resides between the pinned layer and the free layer. The first pinned layer resides between the free layer and the substrate. The second nonmagnetic spacer layer is between the free layer and the second pinned layer. Further, the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of layers which are stacked as a bottom layer, an MTJ layer, and a top layer, patterning the top layer and the MTJ layer using an etch mask pattern to form a top layer pattern and an MTJ pattern, forming a carbon spacer on the sidewalls of the MTJ pattern and the top layer pattern to protect the MTJ pattern and the top layer pattern, and patterning the bottom layer using the carbon spacer and the etch mask pattern as an etch mask to form a bottom layer pattern.

Abstract: A non-volatile memory (NVM) system compatible with double data rate, single data rate, or other high speed serial burst operation. The NVM system includes input and output circuits adapted to synchronously send or receive back-to-back continuous bursts of serial data at twice the frequency of any clock input. Each burst is J bits in length. The NVM system includes read and write circuits that are adapted to read or write J bits of data at a time and in parallel, for each of a multitude of parallel data paths. Data is latched such that write time is similar for each bit and is extended to the time it takes to transmit an entire burst. Consequently, the need for small and fast sensing circuits on every column of a memory array, and fast write time at twice the frequency of the fastest clock input, are relieved.

Abstract: A write circuit is adapted to provide a same logical bit to each of a multitude of memory cells for storage. Each of the multitude of memory cells stores either the bit or a complement of the bit in response to the write circuit. A read circuit is adapted to receive the bits stored in the multitude of memory cells and to generate an output value defined by the stored bits in accordance with a predefined rule. The predefined rule may be characterized by a statistical mode of the bits stored in the plurality of memory cells. Storage errors in a minority of the multitude of memory cells may be ignored at the cost of lower memory density. The predefined rule may be characterized by a first weight assigned to bits 1 and a second weight assigned to bits 0.

Abstract: A method and system for providing a magnetic substructure usable in a magnetic device, as well as a magnetic element and memory using the substructure are described. The magnetic substructure includes a plurality of ferromagnetic layers and a plurality of nonmagnetic layers. The plurality of ferromagnetic layers are interleaved with the plurality of nonmagnetic layers. The plurality of ferromagnetic layers are immiscible with and chemically stable with respect to the plurality of nonmagnetic layers. The plurality of ferromagnetic layers are substantially free of a magnetically dead layer-producing interaction with the plurality of nonmagnetic layers. Further, the plurality of nonmagnetic layers induce a perpendicular anisotropy in the plurality of ferromagnetic layers. The magnetic substructure is configured to be switchable between a plurality of stable magnetic states when a write current is passed through the magnetic substructure.

Abstract: A magnetic device including a magnetic element is described. The magnetic element includes a fixed layer having a fixed layer magnetization, a spacer layer that is nonmagnetic, and a free layer having a free layer magnetization. The free layer is changeable due to spin transfer when a write current above a threshold is passed through the first free layer. The free layer is includes low saturation magnetization materials.

Abstract: Techniques and magnetic devices associated with a magnetic element that includes a fixed layer having a fixed layer magnetization and perpendicular anisotropy, a nonmagnetic spacer layer, and a free layer having a changeable free layer magnetization and perpendicular anisotropy.

Abstract: Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation.

Abstract: A method and system for providing a magnetic junction usable in a magnetic memory are described. The magnetic junction includes first and second pinned layers, first and second nonmagnetic spacer layers, and a free layer. The first pinned layer has a first pinned layer magnetic moment and is nonmagnetic layer-free. The first nonmagnetic spacer layer resides between the first pinned and free layers. The free layer resides between the first and second nonmagnetic spacer layers. The second pinned layer has a second pinned layer magnetic moment and is nonmagnetic layer-free. The second nonmagnetic spacer layer resides between the free and second pinned layers. The first and second pinned layer magnetic moments are antiferromagnetically coupled and self-pinned. The magnetic junction is configured to allow the free layer to be switched between stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a plurality of nonmagnetic spacer layers, and a plurality of free layers. The free layers are interleaved with the nonmagnetic spacer layers. A first nonmagnetic spacer layer of the nonmagnetic spacer layers is between the free layers and the pinned layer. Each of the free layers is configured to be switchable between stable magnetic states when a write current is passed through the magnetic junction. Each of the free layers has a critical switching current density. The critical switching current density of one of the free layers changes monotonically from the critical switching current density of an adjacent free layer. The adjacent free layer is between the pinned layer and the one of the plurality of free layers.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. At least one of the pinned layer and the free layer includes a magnetic substructure. The magnetic substructure includes at least two magnetic layers interleaved with at least one insertion layer. Each insertion layer includes at least one of Cr, Ta, Ti, W, Ru, V, Cu, Mg, aluminum oxide, and MgO. The magnetic layers are exchange coupled.

Abstract: A method and system for providing a magnetic junction usable in a magnetic memory are described. The magnetic junction includes first and second pinned layers, first and second nonmagnetic spacer layers, and a free layer. The pinned layers are nonmagnetic layer-free and self-pinned. In some aspects, the magnetic junction is configured to allow the free and second pinned layers to be switched between stable magnetic states when write currents are passed therethrough. The magnetic junction has greater than two stable states. In other aspects, the magnetic junction includes at least third and fourth spacer layers, a second free layer therebetween, and a third pinned layer having a pinned layer magnetic moment, being nonmagnetic layer-free, and being coupled to the second pinned layer. The magnetic junction is configured to allow the free layers to be switched between stable magnetic states when write currents are passed therethrough.

Abstract: A method and system for providing a magnetic memory are described. The method and system include providing magnetic storage cells, bit lines coupled with the magnetic storage cells, preset lines, and word lines coupled with the magnetic storage cells. Each magnetic storage cell includes magnetic element(s). The bit lines drive write current(s) through selected storage cell(s) of the magnetic storage cells to write to the selected storage cell(s). The preset lines drive preset current(s) in proximity to but not through the selected storage cell(s). The preset current(s) generate magnetic field(s) to orient the magnetic element(s) of the selected storage cell(s) in a direction. The word lines enable the selected storage cell(s) for writing. Either the bit lines reside between the preset lines and the storage cells or the preset lines reside between the storage cells and on a storage cell side of the bit lines.

Abstract: Techniques and magnetic devices associated with a magnetic element are described that includes a presetting fixed layer having a presetting fixed layer magnetization, a free layer having a changeable free layer magnetization, and a fixed layer having a fixed layer magnetization, where a presetting current pulse applied between the presetting fixed layer and free layer operates to preset the free layer magnetization in advance of a write pulse. Techniques and magnetic devices associated with a magnetic element are described that includes a first terminal, a first magnetic tunnel junction, a second terminal, a second magnetic tunnel junction, and a third terminal, where a current pulse applied between the first and second terminal operate to switch the state of the first magnetic tunnel junction and a current applied between the second and third terminal operate to switch the state of the second magnetic tunnel junction.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has an easy cone magnetic anisotropy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A method and system for providing a magnetic memory are described. The method and system include providing memory array tiles (MATs), intermediate circuitry, global bit lines, global word lines, and global circuitry. Each MAT includes magnetic storage cells, bit lines, and word lines. Each of the magnetic storage cells includes at least one magnetic element and at least one selection device. The magnetic element(s) are programmable using write current(s) driven through the magnetic element(s). The bit lines and the word lines correspond to the magnetic storage cells. The intermediate circuitry controls read and write operations within the MATs. Each global bit line corresponds to a first portion of the plurality of MATs. Each global word line corresponds to a second portion of the MATs. The global circuitry selects and drives part of the global bit lines and part of the global word lines for the read and write operations.