Abstract: A method and system for providing a magnetic element are described. The magnetic element includes pinned and free layers, a nonmagnetic spacer layer between the free and pinned layers, and a stability structure. The free layer is between the spacer layer and the stability structure. The free layer has a free layer magnetization, at least one free layer easy axis, and at least one hard axis. The stability structure includes magnetic layers and is configured to decrease a first magnetic energy corresponding to the free layer magnetization being aligned with the at least one easy axis without decreasing a second magnetic energy corresponding to the free layer magnetization being aligned with the at least one hard axis. The magnetic element is configured to allow the free layer magnetization to be switched to between states when a write current is passed through the magnetic element.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has a magnetic anisotropy, at least a portion of which is a biaxial anisotropy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A non-volatile memory array includes a plurality of word-lines and a plurality of columns. One of the columns further includes a bistable regenerative circuit coupled to a first, a second, a third, and a fourth signal lines. The column also includes a non-volatile memory cell having current carrying terminals coupled to the first and second signal lines and a control terminal coupled to one of the plurality of word-lines. The column further includes a first transistor and a second transistor. The first transistor is coupled to the first terminal of the bistable regenerative circuit, and to a fifth signal line. The second transistor has a first current carrying terminal coupled to the second terminal of the bistable regenerative circuit, and a second current carrying terminal coupled to a sixth signal line. The gate terminals of the first and second transistors are coupled to a seventh signal line.

Abstract: A write circuit is adapted to provide a same logical bit to each of a multitude of memory cells for storage. Each of the multitude of memory cells stores either the bit or a complement of the bit in response to the write circuit. A read circuit is adapted to receive the bits stored in the multitude of memory cells and to generate an output value defined by the stored bits in accordance with a predefined rule. The predefined rule may be characterized by a statistical mode of the bits stored in the plurality of memory cells. Storage errors in a minority of the multitude of memory cells may be ignored at the cost of lower memory density. The predefined rule may be characterized by a first weight assigned to bits 1 and a second weight assigned to bits 0.

Abstract: A magnetic memory device and a method for manufacturing the same are disclosed. The magnetic memory device includes a plurality of gates formed on a semiconductor substrate, a source line connected to a source/drain region shared between the gates neighboring with each other, a plurality of magnetic tunnel junctions connected to non-sharing source/drain regions of the gates on a one-to-one basis, and a bit line connected to the magnetic tunnel junctions. The magnetic memory device applies a magnetic memory cell to a memory so as to manufacture a higher-integration magnetic memory, and uses the magnetic memory cell based on a transistor of a DRAM cell, resulting in an increase in the availability of the magnetic memory.

Abstract: A system implementing parallel memory error detection and correction divides data having a word length of K bits into multiple N-bit portions. The system has a separate error processing subsystem for each of the N-bit portions, and utilizes each error processing subsystem to process the associated N-bit portion of the K-bit input data. During memory write operations, each error processing subsystem generates parity information for the N-bit data, and writes the N-bit data and parity information into a separate memory array that corresponds to the error processing subsystem. During memory read operations, each error processing subsystem reads N-bits of data and the associated parity information. If, based on the parity information, an error is detected from the N-bit data, the error processing subsystem attempts to correct the error. The corrected N-bit data from each of the error processing subsystems are combined to reproduce the K-bit word.

Abstract: A magnetic memory device and a method for manufacturing the same are disclosed. The magnetic memory device includes a plurality of gates formed on a semiconductor substrate, a source line connected to a source/drain region shared between the gates neighboring with each other, a plurality of magnetic tunnel junctions connected to non-sharing source/drain regions of the gates on a one-to-one basis, and a bit line connected to the magnetic tunnel junctions. The magnetic memory device applies a magnetic memory cell to a memory so as to manufacture a higher-integration magnetic memory, and uses the magnetic memory cell based on a transistor of a DRAM cell, resulting in an increase in the availability of the magnetic memory.

Abstract: A method and system for providing a magnetic junction are described. The method and system include providing a free layer, a symmetry filter, and a pinned layer. The free layer has a first magnetic moment switchable between stable states when a write current is passed through the magnetic junction. The symmetry filter transmits charge carriers having a first symmetry with higher probability than charge carriers having another symmetry. The pinned layer has a second magnetic moment pinned in a direction. The symmetry filter resides between the free layer and the pinned layer. At least one of the free layer and the pinned layer lies in a plane, has the charge carriers of the first symmetry in a spin channel at a Fermi level, lacks the charge carriers of the first symmetry at the Fermi level in another spin channel, and has a nonzero magnetic moment component perpendicular to the plane.

Abstract: A method and system for providing a logic device are described. The logic device includes a plurality of magnetic input/channel regions, at least one magnetic sensor region, and at least one sensor coupled with the at least one magnetic sensor region. Each of the magnetic input/channel regions is magnetically biased in a first direction. The magnetic sensor region(s) are magnetically biased in a second direction different from the first direction such that at least one domain wall resides in the magnetic input/channel regions if the logic device is in a quiescent state. The sensor(s) output a signal based on a magnetic state of the magnetic sensor region(s). The input/channel regions and the magnetic sensor region(s) are configured such that the domain wall(s) may move into the magnetic sensor region(s) in response to a logic signal being provided to at least a portion of the magnetic input regions.

Abstract: Circuit includes, in part, random access memory cells, column decoders, row decoders, and write driver circuit. Driver circuit is responsive to data and control signals. Writing data includes multiple write phases, each phase driving predetermined current through selected cell by driver setting predetermined voltages to first and second lines. Voltages are in sets such that sequential voltages of each set correspond to respective phase. During writing of first data to selected cell, driver circuit causes first signal line to be at second voltage set and second signal line to be at first voltage set. Second voltage set is greater than first voltage set. During writing of second data to selected cell, driver cause first signal line to be at third voltage set and second signal line to be at fourth voltage set. Third voltage set is smaller than the fourth voltage set.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a plurality of nonmagnetic spacer layers, and a plurality of free layers. The free layers are interleaved with the nonmagnetic spacer layers. A first nonmagnetic spacer layer of the nonmagnetic spacer layers is between the free layers and the pinned layer. Each of the free layers is configured to be switchable between stable magnetic states when a write current is passed through the magnetic junction. Each of the free layers has a critical switching current density. The critical switching current density of one of the free layers changes monotonically from the critical switching current density of an adjacent free layer. The adjacent free layer is between the pinned layer and the one of the plurality of free layers.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. At least one of the pinned layer and the free layer includes a magnetic substructure. The magnetic substructure includes at least two magnetic layers interleaved with at least one insertion layer. Each insertion layer includes at least one of Cr, Ta, Ti, W, Ru, V, Cu, Mg, aluminum oxide, and MgO. The magnetic layers are exchange coupled.

Abstract: Techniques and device designs associated with devices having magnetically shielded magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves that are configured to operate based on spin-transfer torque switching.

Abstract: A method and system for providing a magnetic element and a magnetic memory utilizing the magnetic element are described. The magnetic element is used in a magnetic device that includes a contact electrically coupled to the magnetic element. The method and system include providing pinned, nonmagnetic spacer, and free layers. The free layer has an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy corresponding to a perpendicular anisotropy energy that is less than the out-of-plane demagnetization energy. The nonmagnetic spacer layer is between the pinned and free layers. The method and system also include providing a perpendicular capping layer adjoining the free layer and the contact. The perpendicular capping layer induces at least part of the perpendicular magnetic anisotropy in the free layer. The magnetic element is configured to allow the free layer to be switched between magnetic states when a write current is passed through the magnetic element.

Abstract: A magnetic memory device and a method for manufacturing the same are disclosed. The magnetic memory device includes a plurality of gates formed on a semiconductor substrate, a source line connected to a source/drain region shared between the gates neighboring with each other, a plurality of magnetic tunnel junctions connected to non-sharing source/drain regions of the gates on a one-to-one basis, and a bit line connected to the magnetic tunnel junctions. The magnetic memory device applies a magnetic memory cell to a memory so as to manufacture a higher-integration magnetic memory, and uses the magnetic memory cell based on a transistor of a DRAM cell, resulting in an increase in the availability of the magnetic memory.

Abstract: Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has an easy cone magnetic anisotropy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A method and system for providing a magnetic junction usable in a magnetic memory are described. The magnetic junction includes first and second pinned layers, first and second nonmagnetic spacer layers, and a free layer. The first pinned layer has a first pinned layer magnetic moment and is nonmagnetic layer-free. The first nonmagnetic spacer layer resides between the first pinned and free layers. The free layer resides between the first and second nonmagnetic spacer layers. The second pinned layer has a second pinned layer magnetic moment and is nonmagnetic layer-free. The second nonmagnetic spacer layer resides between the free and second pinned layers. The first and second pinned layer magnetic moments are antiferromagnetically coupled and self-pinned. The magnetic junction is configured to allow the free layer to be switched between stable magnetic states when a write current is passed through the magnetic junction.

Abstract: Techniques and magnetic devices associated with a magnetic element that includes a fixed layer having a fixed layer magnetization and perpendicular anisotropy, a nonmagnetic spacer layer, and a free layer having a changeable free layer magnetization and perpendicular anisotropy.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has a magnetic anisotropy, at least a portion of which is a biaxial anisotropy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.