Abstract: A collapsible camp stove having a cover, a chassis having a fuel burner and a pot support; and the pot support and the chassis and the cover are all pivotally interconnected to one another in a parallelogram structure wherein pivotal opening of the cover relative to the chassis causes the pot support to raise upwardly away from a top surface of the chassis while the pot support continuously remains parallel to the top surface of the chassis.

Abstract: A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.

Abstract: A material handling system has an input conduit section 12 having an input cross-sectional shape, an output conduit section 14 having an output cross-sectional shape that is different than the input cross-sectional shape, and a transition adaptor 18 connecting the input conduit section 12 and the output conduit section providing a transition between the input and output cross-sectional shapes. The transition adaptor includes a crown piece 20 that has an outer end having an elliptical sectional shape and an inner end. The transition adaptor includes a box piece 30 that has an inner end and an outer end 32 having a rectangular sectional shape, wherein the inner end of the crown piece mates with the inner end of the box piece. The box piece is formed by a first box half and a second box half 42, wherein each box half 40 is formed from a flat piece of metal and is formed by bending the box half 40 about bend lines.

Abstract: An animal house climate control system uses a method for operating a baffle of an air inlet of an animal house with a motor using timed inlet control. The method includes performing a calibration sequence to calculate opening velocity and opening inertia values and closing velocity and closing inertia values. The method also includes moving the baffle from an initial position to a final position by calculating a calculated power on time for the motor using the opening inertia or closing inertia values. The method can also include calculating a real position error value by comparing the calculated on time for the motor and a measured on time for the motor and using the real position error value to calculate adjusted opening and closing velocity values.

Abstract: A storage array for computational memory cells formed as a memory/processing array provides storage of the data without using the more complicated computational memory cells for storage. The storage array may have multiple columns of the storage cells coupled to a column of the computational memory cells. The storage array may have ECC circuitry.

Abstract: A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Abstract: A poultry nesting system has a nest house with an adjacent platform raised above the surface of the surrounding substrate. The platform has an upper surface and at least a portion of a perimeter of the platform comprises a wire mesh covering a space between the substrate and the upper surface. The wire mesh is formed by a plurality of strands including an upper strand and a lower strand. At least a portion of the upper surface of the platform is supported by a plurality of platform floor supports positioned on a perimeter of the platform. Each of the plurality of platform floor supports includes a bracing member, an upper cap on an upper end of the bracing member and a lower cap on a lower end of the bracing member. The upper cap has an attachment mechanism on an upper portion thereof configured to interact with the upper surface to lock the platform floor support to the upper surface of the platform such that the platform floor support supports the upper surface in its raised position above the substrate.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.

Abstract: A memory device includes a memory array of non-volatile memory cells arranged in rows and columns and responder signal circuitry. The responder signal circuitry performs a calculation on a row of the memory array and generates a responder signal indicating that there is at least one cell in the row having a predefined value.

Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Abstract: A rotary module for a measuring device of an accelerator facility includes a first radial bearing including a first bearing side configured to be paired with an accelerator-side flange connection and further including a second bearing side configured to receive the measuring device on the first radial bearing in a bearing manner such that the measuring device is connected to the accelerator facility by the first radial bearing; and a drive configured to control a rotational movement of the measuring device about an axis of rotation.

Abstract: A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory. Thus, when data words are transferred between storage memory and the processing array, a mechanism orthogonally transposes the data words.

Abstract: A method for an associative memory array includes storing each column of a matrix in an associated column of the associative memory array, where each bit in row j of the matrix is stored in row R-matrix-row-j of the array, storing a vector in each associated column, where a bit j from the vector is stored in an R-vector-bit-j row of the array. The method includes simultaneously activating a vector-matrix pair of rows R-vector-bit-j and R-matrix-row-j to concurrently receive a result of a Boolean function on all associated columns, using the results to calculate a product between the vector-matrix pair of rows, and writing the product to an R-product-j row in the array.

Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.