Abstract: A bin monitoring system is useable with an elevated feed bin having a plurality of legs that support the bin above a pad so that each leg is connected to the pad through a load cell. The system includes an inner leg mount configured to be attached to a leg, the inner leg mount having an upper portion, and an outer bracket mounted on the load cell. The outer bracket receives the inner leg mount such that a bolt aperture in the outer bracket aligns with a bolt aperture in the upper portion of the inner leg mount and is secured with a threaded bolt. Rotation of the threaded bolt moves the inner leg mount toward the outer bracket to lift the leg so that the leg is supported by the load cell.

Abstract: A method and a system for selecting items one by one from a set of items in an associative memory array includes determining a density of the set, if the density is sparse, repeatedly performing an extreme item select (EIS) method to select a next one of the elected items from the set and removing the next one from the set to create a next set, and if the density is not sparse, performing a next index select (NIS) method to create a linked list of the elected items and to repeatedly select a next elected item from the set. An associative memory array includes a plurality of associative memory cells arranged in rows and columns where each first cell in a first row and in a first column has access to a content of a second cell in a second row in an adjacent column.

Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Abstract: A method for an associative memory device includes dividing a multi-bit mantissa A of a number X to a plurality of smaller partial mantissas Aj, offline calculating a plurality of partial exponents F(Aj) for each possible value of each partial mantissa Aj and storing the plurality of partial exponents F(Aj) in a look up table (LUT) of the associative memory device. A system includes an associative memory array to store a plurality of partial mantissas Ai of a mantissa A of a number X and an exponent calculator to utilize the partial mantissas to compute e in the power of X.

Abstract: An ultra low VDD memory cell has a ratioless write port. In some embodiments, the VDD operation level can be as low as the threshold voltage of NMOS and PMOS transistors of the cell.

Abstract: A method for finding an extreme value among a plurality of numbers in an associative memory includes creating a spread-out representation (SOR) for each number of the plurality of numbers, storing each SOR in a column of the associative memory array and performing a horizontal bit-wise Boolean operation on rows of the associative memory array to produce an extreme SOR (ESOR) having the extreme value. A system for finding an extreme value includes an associative memory array to store the plurality of numbers, each number storable in a column; a spread-out representation (SOR) creator to create a SOR for each number of the plurality of numbers and to store each SOR in a column of the associative memory array, and an extreme SOR (ESOR) finder to find an extreme value using a horizontal bit-wise Boolean operation on rows of the associative memory array storing bits of the SORs.

Abstract: A method includes determining a set of k extreme values of a dataset of elements in a constant time irrespective of the size of the dataset. A method creates a set of k indicators, each indicator associated with one multi-bit binary number in a large dataset of multi-bit binary numbers. The method includes arranging the multi-bit binary numbers such that each bit n of each said multi-bit binary number is located in a different row n of an associative memory array, starting from a row storing a most significant bit (MSB), adding an indicator to the set for each multi-bit binary number having a bit with an extreme value in the row and continuing the adding until said set contains k indicators.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A memory device includes a non-destructive memory array that includes memory cells arranged in rows and columns. The array includes a plurality of word lines, first bit lines and second bit lines, a NOR gate per column Each word line activates memory cells in a row and thereby establishes an activated row. First bit lines and second bit lines connect memory cells in columns, each first bit line provides the result of a Boolean AND operation between data stored in the first activated row and data stored in the second activated row. Each second bit line provides the result of a Boolean NOR operation between data stored in the first activated row and data stored in the second activated row. Each per-column NOR gate is connected to the first and second bit lines of each column and compares data stored in the first activated row with data stored in the second activated row.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Abstract: An in-memory multiplier-accumulator includes a memory array, a multi-bit multiplier and a multi-bit layered adder. The memory array has a multiplicity of rows and columns, each column being divided into a plurality of bit line processors and each bit line processor operating on its associated pair of input values. The multi-bit multiplier utilizes each bit line processor to multiply the associated pair of input values in each bit line processor to generate multiplication results. The multi-bit layered adder accumulates the multiplication results of each column of bit line processors.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory. Thus, when data words are transferred between storage memory and the processing array, a mechanism orthogonally transposes the data words.

Abstract: A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability for selected write data in a bit line section to be logically combined (e.g. logically ANDed) with the read result on a read bit line, as if the write data were the read data output of another computational memory cell being read during the read operation. When accumulation logic is implemented in the bit line sections, the implementation and utilization of additional read logic circuitry provides a mechanism for selected write data in a bit line section to be used as the data with which the read result on the read bit line accumulates, before the newly accumulated result is captured and stored in the bit line section's read register.

Abstract: A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.

Abstract: A method for use in an associative memory device when multiplying by a sparse matrix includes storing only non-zero elements of the sparse matrix in the associative memory device as multiplicands. The storing includes locating the non-zero elements in computation columns of the associative memory device according to linear algebra rules along with their associated multiplicands such that a multiplicand and a multiplier of each multiplication operation to be performed are stored in a same computation column. The locating locates one of the non-zero elements in more than one computation column if one of the non-zero elements is utilized in more than one multiplication operation.