Abstract: The Synchronous Packet Manager is the interface for switching synchronous data between a data terminal equipment and a combination data and telephone switching system in a proprietary packet format. A first microprocessor controlled circuit controls data to be received from the switching system or forwarded to it and communicates with a second microprocessor controlled circuit for controlling data to or from a terminal equipment via a common memory.

Abstract: This circuitry permits equal access to a shared resource by a number of central processing units (CPUs). In a multiple CPU arrangement, common resource contention problems arise, when several CPUs attempt to access the common resource. To resolve these contention problems, this circuitry is an improvement to arbitration ring circuitry. The circuitry of this invention permits each of the CPUs equal access to the common resource during situations in which each CPU is constantly generating requests (high bandwidth utilization) for access to the common resource. This invention is particularly useful for systems in which a large number of CPUs must have their local memory rapidly reloaded from a common memory source. Reloading procedures for large numbers of CPUs rquire up to an hour. By employing the present invention, these reloading times can be cut from one hour to approximately 5 minutes.

Abstract: This circuitry permits equal access to a shared resource by a number of central processing units (CPUs). In a multiple CPU arrangement, common resource contention problems arise, when several CPUs attempt to access the common resource. To resolve these contention problems, this circuitry is an improvement to arbitration ring circuitry. The circuitry of this invention permits each of the CPUs equal access to the common resource during situations in which each CPU is constantly generating requests (high bandwidth utilization) for access to the common resource. This invention is particularly useful for systems in which a large number of CPUs must have their local memory rapidly reloaded from a common memory source. Reloading procedures for large numbers of CPUs require up to an hour. By employing the present invention, these reloading times can be cut from one hour to approximately 5 minutes.

Abstract: A TTL-to-CMOS converter consists of a plurality of N-channel and P-channel MOS transistors, each of which is fabricated so as to have a predetermined channel Width-to-Length ratio (W/L). The transistors are arranged to include an input complementary pair for accepting TTL-level signals and an output complementary pair for providing CMOS-level signals. An N-channel tracking transistor is coupled between the drain electrodes of the P-channel and N-channel transistors of the input complementary pair. The (W/L) of the tracking transistor is approximately 1/8 to to 1/7 times the (W/L) of the N-channel transistor of the input complementary pair. This arrangement establishes a converter switch point with a significantly greater degree of accuracy than otherwise attainable. A pull-up transistor has a gate electrode coupled to the input terminal of the input complementary pair and a drain electrode coupled to the input electrode of the output complementary pair.

Abstract: A bidirectional amplifier for use in a transmission line, that utilizes a pair of interconnected bridge circuits including isolation transformers and a pair of unidirectional amplifiers. The transmission in each direction uses a single amplifier to amplify the signal for a particular direction of transmission without effecting the other amplifier.

Abstract: This method is a scheme for suppressing excessive amounts of logic zeros transmitted via T-carrier line facilities between switching systems or channel banks. This scheme provides proper zero bit suppression for alternating mark inversion signalling (AMI). A proper AMI signal contains no more than 15 consecutive logic zero bit positions. This scheme provides for encoding and decoding a 4 frame octet group of an extended superframe. Logic ones are introduced into octets which would otherwise violate the AMI signalling rules. These logic ones are then removed by the receiving system and replaced with the indicated all zero octets before being given to down stream processing. Intermediate storage octets are utilized to contain addresses of an all zero octet. This scheme provides for minimal buffering at the encoding system, which facilitates error detection and correction by the decoding system.

Abstract: This method is a scheme for suppressing excessive amounts of logic zeros transmitted via T-carrier line facilities between switching systems or channel banks. This scheme provides proper zero bit suppression for alternating mark inversion signalling (AMI). A proper AMI signal contains no more than 15 consecutive logic zero bit positions. This scheme provides for encoding and decoding a 4 frame octet group of an extended superframe. Logic ones are introduced into octets which would otherwise violate the AMI signalling rules. These logic ones are then removed by the receiving system and replaced with the indicated all zero octets before being given to down stream processing. This scheme provides for minimal buffering at the encoding system, which facilitates error detection and correction by the decoding system.

Abstract: A laser DC bias controller is disclosed for controlling and monitoring the laser of a fiber-optic transmitter. The arrangement comprises an optical power monitor including a light detector for converting the light output by the laser into photo current. The photo current is converted by the optical power monitor into a voltage representation of the magnitude of the light output by the laser. The voltage representation is output to a DC constant current source which uses the voltage to provide operating current to the laser of sufficient magnitude to keep the laser operating at a set output level. A transmit data detector monitors the incoming data signals to the fiber optic transmitter and outputs to the optical power monitor a current signal which indicates a failure of the data signal. The optical power monitor converts the current signal to a voltage representation which is output to the DC constant current source.

Abstract: A method for generating additive combinations of PCM voice samples separates the samples into magnitude portions and sign portions. The magnitude portion of each PCM voice sample is converted from compressed PCM form to linear form. The magnitudes of the two voice samples, in linear form, along with their respective signs are added together to form a resultant linear value. If there is any overflow as a result of the addition, the resultant value is truncated so as not to exceed a maximum allowable value. The resultant value is then converted from linear form to compressed PCM form along with the proper sign. These steps are iterated for each possible value of the input PCM voice samples. These resultant values are stored in a storage medium for rapid on-line use by a switching system. Off-line generation of combined PCM samples saves system real time as compared to generating these combinations on-line in real time.

Abstract: This method is a scheme for suppressing excessive amounts of logic zeros transmitted via T-carrier line facilities between switching systems or channel banks. This scheme provides proper zero bit suppression for alternating mark inversion signalling (AMI). A proper AMI signal contains no more then 15 consecutive logic zero bit positions. In addition, a proper AMI signal should contain a logic 1 density of an average of one logic 1 per 8-bits of information over every consecutive 3 octet group. This scheme provides for encoding and decoding a 4 frame octet group of an extended superframe. Logic ones are introduced into octets which would otherwise violate the AMI signalling rules. These logic ones are then removed by the receiving system and replaced with the indicated all zero octets before being given to down stream processing.

Abstract: A substrate connector guide for installing and electrically connecting an electrical substrate to a carrier substrate. The substrate connector guide includes a plurality of guide rails mounted on the perimeter edge of the electronical substrate and at least a first electrical connector mounted transversely between the guide rails. First and second substrate guides are mounted to the carrier substate in a spaced and parallel relationship to the other. Each substrate guide includes a channel extending longitudinally along a substrate guide inner side, from an open end to a top guide. The channel is further defined by a top surface and a plurality of drop guides which in turn form a plurality of slots. At least a second electrical connector is mounted and electrically connected to the carrier substrate between the first and second substrate guides.

Abstract: A substrate connector guide for installing and electrically connecting an electrical substrate to a carrier substrate. The substrate connector guide includes a plurality of guide rails mounted on the perimeter edge of the electrical substrate and at least a first electrical connector mounted transversely between the guide rails. First and second substrate guides are mounted to the carrier substrate in a spaced and parallel relationship to the other. Each substrate guide includes a channel extending longitudinally along a substrate guide inner side, from an open end to a top guide. The channel is further defined by a top surface and a plurality of drop guides which in turn form a plurality of slots. At least a second electrical connector is mounted and electrically connected to the carrier substrate between the first and second substrate guides.

Abstract: This circuit facilitates the synchronization of two copies of digital control units. These digital control units control a number of digital spans. One copy of this circuit is active at any one particular time. This one copy drives all the remaining circuitry of the digital span interface for both copies of the digital control unit. The other copy of this circuit is typically in the ready-standby mode. It is not actively driving the remainder of the circuitry within its own copy. When one copy of the digital control unit is brought on-line, a framing operation must be performed to determine the proper framing bit for both copies. Circuitry in the cross-copy data path monitors an attempt to synchronize the two digital control unit copies. The data which is sent cross-copy is modified so that all data bits are at logic 1, except for a bit which the active copy believes is the proper S-bit or framing bit.

Abstract: A dynamic RAM memory refresh circuit is used with a microprocessor. In a small telecommunication switching system, a microprocessor shares access to memory with the dynamic RAM refresh circuit. Since circuitry size is of paramount importance, this circuit may be implemented with CMOS gate array technology. Since memory access is shared by the microprocessor and the dynamic RAM refresh circuit, processor through-put is affected. However, due to the speed of the dynamic RAM refresh circuit, the microprocessor real-time through-put is degraded only from 2 to 5 percent. A row of dynamic RAM memory is refreshed during each memory access by the refresh circuit, so that during a 2 millisecond inteval all dynamic RAM memory is refreshed. In addition, the dynamic RAM refresh circuit provides a strapping option to allow operation of the refresh circuit in conjunction with microprocessors of different clock frequency.

Abstract: An interface circuit for transmitting data and voice signals between a CENTREX equipped central office exchange and a remotely located attendant console. The interface circuit includes an analog interface arranged to receive analog voice signals from the attendant console and to convert the analog signals into digital signals for transmission to the central office exchange. Alternatively, digital signals received from the central office exchange are converted to analog voice signals and are transmitted to the attendant console. A digital interface connecting the attendant console and the central office exchange includes an interface controller arranged to control the operation of the digital interface.

Abstract: A printer table including a series of angled jets for sources of air and for sources of vacuum and also including a set of locating pins. The combination enables the use of the directed jets to move a substrate into position for processing and to hold the substrate in position once located by the locating pins with the use of a vacuum. Because the substrates are very thin and the locating pins are very short, the combined use of the vacuum and directing jets effectively permit the substrate to float on air in close proximity to the table surface while not overriding the locating pins.

Abstract: The present method is a decoding scheme for suppressing excessive amount of zeroes transmitted via a T1 line facility. Clear channel transmission capability is provided by this scheme for 32 kb/s or 64 kb/s transmission channels. This scheme provides the proper zero bit suppression for alternating mark inversion signaling (AMI). A proper AMI signal contains no more then 15 consecutive zero bit positions. In addition to meeting the AMI signaling standards, this scheme does not induce any violations of VMR (violation monitor and removal) equipment. Thus, this scheme is transparent to existing line equipment and error monitoring equipment. This scheme provides both a necessary and sufficient method for achieving the AMI signaling requirements during clear channel signaling.

Abstract: A Multiplexer/Demultiplexer for transmitting packetized data between a processor and a Pulse Code Modulation (PCM) bus. First-in First-Out (FIFO) shift registers, serial-to-parallel and parallel-to-serial converters and associated timing and control circuits are utilized to perform the packetized data transmission.