Abstract: A circuit divides pulse code modulation (PCM) samples in D2 format. An exponent subtractor provides the difference of the exponents of the two numbers. A mantissa multiplier circuit determines the quotient by multiplying the mantissa of the PCM sample by an inverted divider. A sign generator provides a sign value for the resultant quotient of the two numbers. A normalizer circuit ensures that the quotient mantissa has a predetermined range of values.

Abstract: The present method is an encoding scheme for suppressing excessive amount of zeroes transmitted via a T1 line facility. Clear channel transmission capability is provided by this scheme for 32 kb/s or 64 kb/s transmission channels. This scheme provides the proper zero bit suppression for alternating mark inversion signaling (AMI). A proper AMI signal contains no more than 15 consecutive zero bit positions. In addition to meeting the AMI signaling standards, this scheme does not induce any violations of VMR (violation monitor and removal) equipment. Thus, this scheme is transparent to existing line equipment and error monitoring equipment. This scheme provides both a necessary and sufficient method for achieving the AMI signaling requirements during clear channel signaling.

Abstract: An address generator which provides addresses for machine storage and software retrieval of computer status information. A counter is used to generate address signals in a descending order until it is disabled by a computer during alarm conditions. Under such conditions the counter provides a bias address for referencing the most recent status word. A gating circuit gates computer generated address signals to an adder circuit during the alarm conditions. The adder circuit adds the computer generated address signals to the counter generated bias signal to provide address signals which reference physical storage locations in a memory.

Abstract: Telecommunication switching systems are typically connected by high-speed digital data spans. These spans may commonly be T1 or T2 carriers using DS1 or DS2 data formats, respectively. These systems may contain duplex digital span control units. The present synchronization arrangement is an additional duplex control circuit. This synchronization arrangement includes a time multiplexed state machine for each copy of the digital span control unit. The state machine monitors data ready signals from its own copy as well as from the other copy of the digital span control unit. Other signals indicate whether the circuit is operating in a simplex or duplex mode and which circuit is the active and which is the standby copy. This circuitry detects whether the data ready signals for each copy are identically synchronized. If these data ready signals are not identically synchronized, then one copy of the circuitry waits a predetermined scan cycle time for the other copy of the circuit to catch up.

Abstract: Telecommunication switching systems are typically connected by high-speed digital data spans. These spans may commonly be T1 or T2 carriers using DS1 or DS2 data formats, respectively. These systems may contain duplex digital span control units. Synchronization circuitry includes a time multiplexed state machine for each copy of the digital span control unit. The state machine monitors framing alarm signals from its own copy as well as from the other copy of the digital span control unit. This circuitry detects whether the framing alarm signals for each copy are identically synchronized. If these framing alarm signals are not identically synchronized, then one copy of the circuitry executes a hold (wait) operation for the other copy of the circuit to perform its reframing operation. For non-error conditions, the wait places the two copies back in synchronization.

Abstract: A Current Reference for providing a feedback signal to a current driver in a current-series, feedback-controlled current source circuit that includes at least one, but more likely more than one, controlled current source. The Current Reference comprises a current mirror having an input transistor coupled to an output transistor in a current mirror configuration. The input transistor of the current mirror is driven by a constant current source, Icc, so that the current mirror output transistor causes a current substantially equal to Icc to flow out of a summing node. A sensing transistor is coupled to a controlled current source for providing a current into the summing node that is representative of the current delivered by the controlled current source. As a result, the current flowing away from the summing node and into a phase inverter is representative of the difference between the delivered current and Icc.

Abstract: This circuit provides for the connection of simplex I/O terminals to duplex processor copies. Each processor copy's configuration provides for a terminal control circuit. These copies of the terminal control circuit are cross connected in order to provide access from each processor to each I/O terminal. Normal operation consists of a particular I/O terminal being operated by one processor copy. If the processor copy corresponding to a particular terminal is faulty or removed from service, that terminal is then automatically cross-connected to the active processor copy and receives output from that processor copy. If one processor copy is out of service, both I/O terminals receive output from the active processor copy. If the I/O terminal which is normally connected to the active processor copy becomes out of service and the other processor copy is out of service, the I/O terminal which is normally connected to the other processor copy will be reconfigured to be connected to the active processor.

Abstract: An integrated circuit includes an interface circuit for coupling with a relative high-level VOICE circuit and a relatively low-level DIALER circuit to a subscriber line. A first shunt transistor is coupled across the telephone line and has its collector current forced by a current sink driven from the VOICE circuit. A second shunt transistor is coupled in a current mirror configuration to the first shunt transistor and supplies current to the DIALER circuitry. The interface circuit includes a saturation prevention circuit coupled to the current sink and to the second shunt transistor for sensing a tendency of the second shunt transistor toward saturation and for increasing the collector current load on that transistor in response. The saturation prevention circuit includes a voltage offset element and a sensing transistor arranged to form a loop with the collector-to-base junction of the second shunt transistor.

Abstract: A semiconductor encapsulating apparatus including a positioning apparatus positioning an encapsulant premold (preformed piece or pellet) in contact with the semiconductor and the curing apparatus through which the semiconductor and encapsulant are passed to cure and thereby encapsulate the semiconductor. The encapsulating apparatus may include a vacuum chamber to degass the encapsulant prior to curing, a robotic arm to position an encapsulant premold in contact with the semiconductor and encapsulant premold forming apparatus including a die engaging a plastically deformable strip to form therein a mold. Also included may be a mold filling dispenser, a mold solidifying bath which may include liquid nitrogen, a solidified premold ejecting roller and a premold storage tray. Also disclosed are roller and spray coating apparatuses adapted to coat an inner surface of the mold with a release agent thereby to promote subsequent premold release.

Abstract: This invention is a circuit for generating a framing pattern consisting of a pseudo random shift register sequence. This circuit utilizes an extremely long framing pattern without either a large amount of memory or the need to receive a large number of bits in order to recognize the framing pattern. The use of lengthy framing patterns minimizes the chance of false framing caused by patterns in bit positions other than the framing bit position.

Abstract: An amplifier having properties of natural side tone balancing based on the utilization of a bridge arrangement, high efficiency with resulting high gain, high AC impedance and compatibility with electret microphones and electret microphone amplifiers. A matched pair of differential transistors arranged as part of a bridge circuit form a detector of the receive signal at one input versus a transmit signal which appears at both inputs in the same phase and therefore is rejected as a common mode signal. The resultant balancing of side tone and high gain finds particular application in telephone networks where the characteristics dictate the need for higher than usual receive gain or for use by auditorially handicapped users over a normal telephone network.

Abstract: A circuit multiplies or divides pulse code modulation (PCM) samples in D2 format. An exponent adder/subtractor provides the sum/difference of the exponents of the two numbers. A mantissa multiplier/divider circuit determines the product/quotient of the two mantissas and a sign generator provides a sign value for the resultant product/quotient of the two numbers. A normalizer circuit ensures that the product/quotient mantissa has a predetermined range of values.

Abstract: A circuit multiplies pulse code modulation (PCM) samples in D2 format. An exponent adder provides the sum of the exponents of the two numbers. A mantissa multiplier circuit determines the product of the two mantissas and a sign generator provides a sign value for the resultant product of the two numbers. A normalizer circuit ensures that the product mantissa has a predetermined range of values.

Abstract: Simplified CCIS (Common Channel Interoffice Signalling) data transfer circuitry is shown for transmitting data between a CCIS central processing unit of a central switching office and a number of terminal equipment controllers, each having a local CPU. The terminal equipment controller operates such equipment as modems of various speed, digital trunks or T1 spans. This design minimizes the amount of circuitry required to transmit CCIS data between central processing units, thereby permitting a more reliable design. This circuit provides a minimal amount of logic required for interprocessor communication. In addition, this circuit minimizes the amount of real time required by each CPU to perform the CCIS data transfer.

Abstract: This invention is a device which permits the percentage of real time consumed by software tasks of a telecommunications switching system or other process controller to be measured and displayed on a percentage meter. The relative percentages of different real time tasks are displayed by the relative intensities of particular lamps mounted on a control panel. The real time usage of non-standard, user defined, software tasks may be selected for display on the meter.

Abstract: An arrangement for initializing an interface circuit connected between a CENTREX equipped central office exchange and a remotely located attendant console. The arrangement includes an operating unit residing in the interface circuit. The operating unit includes a controller connected to memory and to the CENTREX. The controller receives an initialization signal from the CENTREX and returns an initialization in progress signal. Memory verification called next by the controller ascertains if all locations in the memory are operable. The controller sends an error signal to the CENTREX in the event the memory verifications detects an error. Next, interface initialization called by the controller resets and clears a sequential memory and resets and clears a send/receive circuit connected to the controller and the attendant console. Transmission verification called next by the controller checks if the transmit and receive loop between the attendant console and the interface circuit is operable.