Patents Assigned to Gyrfalcon Technology, Inc.
  • Publication number: 20200151558
    Abstract: A system may be configured to obtain a global artificial intelligence (AI) model for uploading into an AI chip to perform AI tasks. The system may implement a training process including receiving updated AI models from one or more client devices, determining a global AI model based on the received AI models from the client devices, and updating initial AI models for the client devices. Each client device may receive an initial AI model and train an updated AI model by training the entire parameters of the AI model together, by training a subset of the parameters of the AI model in a layer by layer fashion, or by training a subset of the parameters by parameter types. Each client device may include one or more AI chips configured to run an AI task to measure performance of an AI model. The AI model may include a convolutional neural network.
    Type: Application
    Filed: February 11, 2019
    Publication date: May 14, 2020
    Applicant: Gyrfalcon Technology Inc.
    Inventors: Yongxiong Ren, Yequn Zhang, Baohua Sun, Xiaochun Li, Qi Dong, Lin Yang
  • Patent number: 10592804
    Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory includes an array of magnetic random access memory (RAM) cells for storing weights (e.g., filter coefficients) and the second memory contains SRAM for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains magnetic RAM cells for storing one-time-programming data for security purpose. The magnetic RAM includes STT-RAM or OST-MRAM in SLC or MLC technology.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: March 17, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Publication number: 20200057932
    Abstract: A system for encoding data in an artificial intelligence (AI) integrated circuit solution may include a processor configured to receive voice data comprising at least a segment of an audio waveform, load the voice data into an input array of a cellular neural network (CeNN) in the AI integrated circuit, load one or more wavelet filters into one or more kernels of the CeNN, and perform one or more operations on the voice data to generate a time-spectral diagram. The time-spectral diagram may include a wavelet transformation of the voice data. Each of the one or more filters respectively represents a frequency. The system may also output a voice recognition result based on the time-spectral. Sample training data may be encoded in a similar manner for training the cellular neural network.
    Type: Application
    Filed: August 16, 2018
    Publication date: February 20, 2020
    Applicant: GYRFALCON TECHNOLOGY INC.
    Inventors: Xiang Gao, Lin Yang
  • Publication number: 20200042888
    Abstract: This disclosure relates to a self-contained and self-sufficient edge device capable of performing processing data sets using a convolutional neural network model without relying on any backend servers. In particularly, the edge device may include non-volatile memory cells for storing a full set of trained model parameters from the convolutional neural network model. The non-volatile memory cells may be based on magnetic random access memory cells and may be embedded on the same semiconductor substrate with a convolutional neural network logic circuit dedicated to parallel forward propagation calculation.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Applicant: Gyrfalcon Technology Inc.
    Inventors: Hualiang YU, Chyu-Jiuh Torng, Daniel H. Liu
  • Patent number: 10552733
    Abstract: CNN (Cellular Neural Networks or Cellular Nonlinear Networks) based digital Integrated Circuit for artificial intelligence contains multiple CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory contains magnetic random access memory (MRAM) cells for storing weights (e.g., filter coefficients) while the second memory is for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains MRAM cells for storing one-time-programming data for security purpose. The second memory contains MRAM cells or static random access memory cells. Each MRAM cell contains a Spin-Orbit-Torque (SOT) based magnetic tunnel junction (MTJ) element.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: February 4, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Daniel Liu
  • Patent number: 10546234
    Abstract: CNN based digital IC for AI contains a number of CNN processing units. A first CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem, which includes a first one-time-programming (OTP) memory for filter coefficients and a second memory for imagery data. A second CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem that includes a first memory for filter coefficients, a second memory for imagery data and a third OTP memory for unique data pattern (e.g., security purpose). Either STT-RAM or OST-MRAM can be configured as different memories of the memory subsystem.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: January 28, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Patent number: 10545693
    Abstract: Embedded memory subsystems in a digital integrated circuit for artificial intelligence are disclosed. A semi-conductor substrate contains CNN processing units. Each CNN processing unit includes CNN logic circuits and an embedded memory subsystem. The memory subsystem includes first embedded memory and second embedded memory. The first embedded memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area with a diameter in a range of 40-120 nm. The second embedded memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area having a diameter in a range of 30-75 nm.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: January 28, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Patent number: 10534996
    Abstract: CNN (Cellular Neural Networks or Cellular Nonlinear Networks) based digital Integrated Circuit for artificial intelligence contains multiple CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory contains magnetic random access memory (MRAM) cells for storing weights (e.g., filter coefficients) while the second memory is for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights or filter coefficients. The memory subsystem may contain a third memory that contains MRAM cells for storing one-time-programming data for security purpose. The second memory contains MRAM cells or static random access memory cells. Each MRAM cell contains a voltage-controlled magnetic anisotropy (VCMA) based magnetic tunnel junction (MTJ) element. Magnetization direction in VCMA based MTJ element can be in-plane or out-of-plane.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: January 14, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Daniel Liu
  • Publication number: 20190363131
    Abstract: This disclosure relates to embedding memories into with logic circuits for improving memory access speed and reducing power consumption. In particular, memories of distinct types embedded with logic circuits on a same semiconductor substrate are disclosed. These memories may include static random access memory, magnetoresistive random access memory, and various types of resistive random access memory. These different types of memories may be combined to form an embedded memory subsystem that provide distinct memory persistency, programmability, and access characteristics tailored for storing different type of data in, e.g., application involving convolutional neural networks.
    Type: Application
    Filed: May 25, 2018
    Publication date: November 28, 2019
    Applicant: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Daniel H. Liu
  • Patent number: 10482374
    Abstract: An ensemble learning based image classification system contains multiple cellular neural networks (CNN) based integrated circuits (ICs) operatively coupling together as a set of base learners of an ensemble for an image classification task. Each CNN based IC is configured with at least one distinct deep learning model in form of filter coefficients. The ensemble learning based image classification system further contains a controller configured as a meta learner of the ensemble and a memory based data buffer for holding various data used in the ensemble by the controller and the CNN based ICs. Various data may include input imagery data to be classified. Various data may also include extracted feature vectors or image classification outputs out of the set of base learners. The extracted feature vectors or image classification outputs are then used by the meta learner to further perform the image classification task.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 19, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Lin Yang, Patrick Z. Dong, Charles Jin Young, Jason Z. Dong, Michael Lin, Baohua Sun
  • Patent number: 10481815
    Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem. A first subsystem includes an array of first magnetic random access memory (RAM) cells for storing weights and an array of second magnetic RAM cells for storing input signals. A second subsystem includes an array of first magnetic RAM cells for storing one-time-programming weights and an array of second magnetic RAM cells for storing input signals. A third subsystem includes an array of first magnetic RAM cells for storing weights, an array of second magnetic RAM cells for storing input signals and an array of third magnetic RAM cells for storing one-time-programming unique data pattern for security identification. Either MLC STT-RAM or MLC OST-MRAM containing at least two MTJ elements can be configured as different memories for forming memory subsystem.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: November 19, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Publication number: 20190348062
    Abstract: A system for encoding data in an artificial intelligence (AI) integrated circuit solution may include a processor configured to receive image/voice data and generate a sequence of two-dimensional (2D) arrays each array being shifted from a preceding 2D array in the sequence by a time difference. The system may load the sequence of arrays into an AI integrated circuit, feed each of the 2D arrays in the sequence into a respective channel in an embedded cellular neural network architecture in the AI integrated circuit. The system may generate an image/voice recognition result from the embedded cellular neural network architecture and output the image/voice recognition result. The sequence of 2D arrays in the image recognition may include a sequence of output images. The sequence of 2D arrays in the voice recognition may include 2D frequency-time arrays. Sample data may be encoded in a similar manner for training the cellular neural network.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 14, 2019
    Applicant: GYRFALCON TECHNOLOGY INC.
    Inventors: Xiang Gao, Lin Yang, Wenhan Zhang
  • Patent number: 10452955
    Abstract: Methods of encoding image data for loading into an artificial intelligence (AI) integrated circuit are provided. The AI integrated circuit may have an embedded cellular neural network for implementing AI tasks based on the loaded image data. An encoding method may apply image splitting, principal component analysis (PCA) or a combination thereof to an input image to generate a plurality of output images. Each output image has a size smaller than the size of the input image. The method may load the output images into the AI chip, execute programming instructions contained in the AI chip to generate an image recognition result based on the at least one of the plurality of output images, and output the image recognition result. The encoding method also trains a convolution neural network (CNN) and loads the weights of the CNN into the AI integrated circuit for implementing the AI tasks.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: October 22, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Xiang Gao, Lin Yang, Wenhan Zhang
  • Patent number: 10445568
    Abstract: Two-dimensional symbols with each containing multiple ideograms for facilitating machine learning are disclosed. Two-dimensional symbol comprises a matrix of N×N pixels of data representing a “super-character”. The matrix is divided into M×M sub-matrices with each of the sub-matrices containing (N/M)×(N/M) pixels. N and M are positive integers or whole numbers, and N is preferably a multiple of M. Each of the sub-matrices represents one ideogram defined in an ideogram collection set. “Super-character” represents at least one meaning each formed with a specific combination of a plurality of ideograms. Ideogram collection set includes, but is not limited to, pictograms, logosyllabic characters, Japanese characters, Korean characters, punctuation marks, numerals, special characters. Logosyllabic characters may contain one or more of Chinese characters, Japanese characters, Korean characters. Features of each ideogram can be represented by more than one layer of two-dimensional symbol.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: October 15, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Lin Yang, Patrick Z. Dong, Baohua Sun
  • Publication number: 20190311246
    Abstract: A system may include a decentralized communication network and multiple processing devices on the network. Each processing device may have an artificial intelligence (AI) chip, the device may be configured to generate an AI model, determine the performance value of the AI model on the AI chip, receive a chain from the network where the chain contains a performance measure. If the performance value of the AI model is better than the performance measure, then the processing device may broadcast the AI model to the network for verification. If the AI model is verified by the network, the device may update the chain with the performance value so that the chain can be shared by the multiple processing devices on the network. Any processing device on the network may also verify an AI model broadcasted by any other device. Methods for generating the AI model are also provided.
    Type: Application
    Filed: April 10, 2018
    Publication date: October 10, 2019
    Applicant: GYRFALCON TECHNOLOGY INC.
    Inventors: Lin Yang, Charles Jin Young, Jason Zeng Dong, Patrick Zeng Dong, Baohua Sun, Yequn Zhang
  • Publication number: 20190311247
    Abstract: A system may include a decentralized communication network and multiple processing devices on the network. Each processing device may have an artificial intelligence (AI) chip, the device may be configured to generate an AI model, determine the performance value of the AI model on the AI chip, receive a chain from the network where the chain contains a performance measure. If the performance value of the AI model is better than the performance measure, then the processing device may broadcast the AI model to the network for verification. If the AI model is verified by the network, the device may update the chain with the performance value so that the chain can be shared by the multiple processing devices on the network. Any processing device on the network may also verify an AI model broadcasted by any other device. Methods for generating the AI model are also provided.
    Type: Application
    Filed: April 10, 2018
    Publication date: October 10, 2019
    Applicant: GYRFALCON TECHNOLOGY INC.
    Inventors: Lin Yang, Charles Jin Young, Jason Zeng Dong, Patrick Zeng Dong, Baohua Sun, Yequn Zhang
  • Patent number: 10417342
    Abstract: A local processing device contains a bus, an input interface and at least one cellular neural networks (CNN) based integrated circuit (IC). The input interface is receiving a 2-D symbol representing a Chinese poetry or verse. The 2-D symbol is a matrix of N×N pixels of K-bit data that contains a “super-character”. The matrix is divided into M×M sub-matrices each containing (N/M)×(N/M) pixels. Each of the sub-matrices represents an ideogram. K, N and M are positive integers, and N is a multiple of M. CNN based IC is configured for understanding semantic meaning of the Chinese poetry or verse within the “super-character” contained in the 2-D symbol. The ideogram is created by embedded fonts of all of the characters contained in a corresponding phrase of the Chinese poetry or verse or is a pictogram representing artistic conception of each sentence of the Chinese poetry or verse.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: September 17, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Lin Yang, Patrick Z. Dong, Baohua Sun
  • Patent number: 10402628
    Abstract: Image classification system contains a CNN based IC configured for extracting features out of input data by performing convolution operations using filter coefficients of ordered convolutional layers and a classifier IC configured for classifying the input data using reduced set of the extracted features based on a light-weight classifier. Light-weight classifier is derived by: training filter coefficients of the ordered convolutional layers using a dataset containing N labeled data, the trained filter coefficients are for the CNN based IC; outputting respective extracted features of the N labeled data after performing convolution operations of ordered convolutional layers using the trained filter coefficients, each labeled data contains X features; creating the reduced set of the extracted features by eliminating those of the X features that contain zeros in at least M of the N labeled data; and adjusting M until the light-weight classifier achieves satisfactory results using the reduced set.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: September 3, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Lin Yang, Patrick Z. Dong, Charles Jin Young, Jason Dong, Wenhan Zhang, Baohua Sun
  • Publication number: 20190267072
    Abstract: An integrated circuit includes an artificial intelligence (AID) logic and an embedded memory coupled to the AID logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Applicant: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong, Daniel H. LIU
  • Patent number: 10387740
    Abstract: A deep learning object detection and recognition system contains a number of cellular neural networks (CNN) based integrated circuits (ICs) operatively coupling together via the network bus. The system is configured for detecting and then recognizing one or more objects out of a two-dimensional (2-D) imagery data. The 2-D imagery data is divided into N set of distinct sub-regions in accordance with respective N partition schemes. CNN based ICs are dynamically allocated for extracting features out of each sub-region for detecting and then recognizing an object potentially contained therein. Any two of the N sets of sub-regions overlap each other. N is a positive integer. Object detection is achieved with a two-category classification using a deep learning model based on approximated fully-connected layers, while object recognition is performed using a local database storing feature vectors of known objects.
    Type: Grant
    Filed: May 19, 2018
    Date of Patent: August 20, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Lin Yang, Patrick Z. Dong, Charles Jin Young, Jason Z. Dong, Wenhan Zhang, Baohua Sun