Abstract: In some examples, given an AI model in floating point, a system may use one or more artificial intelligence (AI) chips to train a global gain vector for use to convert the AI model in floating point to an AI model in fixed point for uploading to a physical AI chip. The system may determine initial gain vectors, and in each of multiple iterations, obtain the performance values of the AI chips based on the gain vectors and update the gam vectors for the next iteration. The gain vectors are updated based on a velocity of gain. The performance value may be based on feature maps of an AI model before and after the converting. The performance value may also be based on interference over a test dataset. Upon completion of the iterations, the system determines the global gain vector that resulted in the best performance value during the iterations.

Abstract: This disclosure relates to testing of integrated artificial intelligence (AI) circuit with embedded memory to improve effective chip yield and to mapping addressable memory segments of the embedded memory to multilayer AI networks at the network level, layer level, parameter level, and bit level based on bit error rate (BER) of the addressable memory segments. The disclosed methods and systems allows for deployment of one or more multilayer AI networks in an AI circuit with sufficient model accuracy even when the embedded memory has an overall BER higher than a preferred overall threshold.

Abstract: A system may include multiple client devices and a processing device communicatively coupled to the client devices. A client device may receive an initial artificial intelligence (AI) model, use a training dataset to perform an AI task, and update its AI model. The client device may verify the performance of the AI task to determine whether to accept or reject its updated AI model. Upon rejection, the client device may repeat updating its AI model until the updated AI model is accepted, or until a stopping criteria is met. The processing device may be configured to update the initial AI models based on the accepted updated AI models obtained in the multiple client devices, and repeat the process for each client device using the updated initial AI models. Training data for each of the client devices may contain a subset shuffled from a larger training dataset.

Abstract: A system may include multiple client devices and a processing device communicatively coupled to the client devices. One or more client devices may implement a greedy approach in searching for an optimal artificial intelligence (AI) model. For example, a client device may use a training dataset to perform an AI task, and update its AI model. The client device may verify the performance of the AI task and determine whether to accept or reject its updated AI model. Upon rejection, the client device may repeat updating its AI model until the updated AI model is accepted, or until a stopping criteria is met. The processing device may be configured to update the initial AI models based on the accepted updated AI models obtained in the multiple client device. Training data for each of the client devices may contain a subset shuffled from a larger training dataset.

Abstract: An image and the maximum number of tokens for a to-be-created image caption are received in a computing system. Font size of graphical image of the token is calculated from the maximum number of tokens and the dimension of desired input image for prediction-style image classification technique. Desired input image is divided into first and second portions. A 2-D symbol is formed by placing a resized image derived from the received image with substantially similar contents in the first portion and by initializing the second portion with blank images. Next token of the image caption is predicted by classifying the 2-D symbol using the prediction-style image classification technique. 2-D symbol is modified by appending the graphical image of just-predicted token to the existing image caption in the second portion, if termination condition for image caption creation is false. Next token is repeatedly predicted until termination condition becomes true.

Abstract: This disclosure relates to testing of integrated artificial intelligence (AI) circuit with embedded memory to improve effective chip yield and to mapping addressable memory segments of the embedded memory to multilayer AI networks at the network level, layer level, parameter level, and bit level based on bit error rate (BER) of the addressable memory segments. The disclosed methods and systems allows for deployment of one or more multilayer AI networks in an AI circuit with sufficient model accuracy even when the embedded memory has an overall BER higher than a preferred overall threshold.

Abstract: This disclosure relates to artificial intelligence (AI) circuits with embedded memory for storing trained AI model parameters. The embedded memory cell structure, device profile, and/or fabrication process are designed to generate binary data access asymmetry and error rate asymmetry between writing binary zeros and binary ones that are adapted to and compatible with a binary data asymmetry of the trained model parameters and/or a bit-inversion tolerance asymmetry of the AI model between binary zeros and ones. The disclosed method and system improves predictive accuracy and memory error tolerance without significantly reducing an overall memory error rate and without relying on memory cell redundancy and error correction codes.

Abstract: An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.

Abstract: A device for obtaining a local optimal AI model may include an artificial intelligence (AI) chip and a processing device configured to receive a first initial AI model from the host device. The device may load the initial AI model into the AI chip to determine a performance value of the AI model based on a dataset, and determine a probability that a current AI model should be replaced by the initial AI model. The device may determine, based on the probability, whether to replace the current AI model with the initial AI model. If it is determined that the current AI model be replaced, the device may replace the current AI model with the initial AI model. The device may repeat the above processes and obtain a final current AI model. The device may transmit the final current AI model to the host device.

Abstract: A system may include multiple client devices and a processing device communicatively coupled to the client devices. Each client device includes an artificial intelligence (AI) chip and is configured to generate an AI model. The processing device may be configured to (i) receive a respective AI model and an associated performance value of the respective AI model from each of the plurality of client devices; (ii) determine an optimal AI model based on the performance values associated with the respective AI models from the plurality of client devices; and (iii) determine a global AI model based on the optimal AI model. The system may load the global AI model into an AI chip of a client device to cause the client device to perform an AI task based on the global AI model in the AI chip. The AI model may include a convolutional neural network.

Abstract: A system may be configured to obtain a global artificial intelligence (AI) model for uploading into an AI chip to perform AI tasks. The system may implement a training process including receiving updated AI models from one or more client devices, determining a global AI model based on the received AI models from the client devices, and updating initial AI models for the client devices. Each client device may receive an initial AI model and train an updated AI model by training the entire parameters of the AI model together, by training a subset of the parameters of the AI model in a layer by layer fashion, or by training a subset of the parameters by parameter types. Each client device may include one or more AI chips configured to run an AI task to measure performance of an AI model. The AI model may include a convolutional neural network.

Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory includes an array of magnetic random access memory (RAM) cells for storing weights (e.g., filter coefficients) and the second memory contains SRAM for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains magnetic RAM cells for storing one-time-programming data for security purpose. The magnetic RAM includes STT-RAM or OST-MRAM in SLC or MLC technology.

Abstract: A system for encoding data in an artificial intelligence (AI) integrated circuit solution may include a processor configured to receive voice data comprising at least a segment of an audio waveform, load the voice data into an input array of a cellular neural network (CeNN) in the AI integrated circuit, load one or more wavelet filters into one or more kernels of the CeNN, and perform one or more operations on the voice data to generate a time-spectral diagram. The time-spectral diagram may include a wavelet transformation of the voice data. Each of the one or more filters respectively represents a frequency. The system may also output a voice recognition result based on the time-spectral. Sample training data may be encoded in a similar manner for training the cellular neural network.

Abstract: This disclosure relates to a self-contained and self-sufficient edge device capable of performing processing data sets using a convolutional neural network model without relying on any backend servers. In particularly, the edge device may include non-volatile memory cells for storing a full set of trained model parameters from the convolutional neural network model. The non-volatile memory cells may be based on magnetic random access memory cells and may be embedded on the same semiconductor substrate with a convolutional neural network logic circuit dedicated to parallel forward propagation calculation.

Abstract: CNN (Cellular Neural Networks or Cellular Nonlinear Networks) based digital Integrated Circuit for artificial intelligence contains multiple CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory contains magnetic random access memory (MRAM) cells for storing weights (e.g., filter coefficients) while the second memory is for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains MRAM cells for storing one-time-programming data for security purpose. The second memory contains MRAM cells or static random access memory cells. Each MRAM cell contains a Spin-Orbit-Torque (SOT) based magnetic tunnel junction (MTJ) element.

Abstract: CNN based digital IC for AI contains a number of CNN processing units. A first CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem, which includes a first one-time-programming (OTP) memory for filter coefficients and a second memory for imagery data. A second CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem that includes a first memory for filter coefficients, a second memory for imagery data and a third OTP memory for unique data pattern (e.g., security purpose). Either STT-RAM or OST-MRAM can be configured as different memories of the memory subsystem.

Abstract: Embedded memory subsystems in a digital integrated circuit for artificial intelligence are disclosed. A semi-conductor substrate contains CNN processing units. Each CNN processing unit includes CNN logic circuits and an embedded memory subsystem. The memory subsystem includes first embedded memory and second embedded memory. The first embedded memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area with a diameter in a range of 40-120 nm. The second embedded memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area having a diameter in a range of 30-75 nm.

Abstract: CNN (Cellular Neural Networks or Cellular Nonlinear Networks) based digital Integrated Circuit for artificial intelligence contains multiple CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory contains magnetic random access memory (MRAM) cells for storing weights (e.g., filter coefficients) while the second memory is for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights or filter coefficients. The memory subsystem may contain a third memory that contains MRAM cells for storing one-time-programming data for security purpose. The second memory contains MRAM cells or static random access memory cells. Each MRAM cell contains a voltage-controlled magnetic anisotropy (VCMA) based magnetic tunnel junction (MTJ) element. Magnetization direction in VCMA based MTJ element can be in-plane or out-of-plane.

Abstract: This disclosure relates to embedding memories into with logic circuits for improving memory access speed and reducing power consumption. In particular, memories of distinct types embedded with logic circuits on a same semiconductor substrate are disclosed. These memories may include static random access memory, magnetoresistive random access memory, and various types of resistive random access memory. These different types of memories may be combined to form an embedded memory subsystem that provide distinct memory persistency, programmability, and access characteristics tailored for storing different type of data in, e.g., application involving convolutional neural networks.

Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem. A first subsystem includes an array of first magnetic random access memory (RAM) cells for storing weights and an array of second magnetic RAM cells for storing input signals. A second subsystem includes an array of first magnetic RAM cells for storing one-time-programming weights and an array of second magnetic RAM cells for storing input signals. A third subsystem includes an array of first magnetic RAM cells for storing weights, an array of second magnetic RAM cells for storing input signals and an array of third magnetic RAM cells for storing one-time-programming unique data pattern for security identification. Either MLC STT-RAM or MLC OST-MRAM containing at least two MTJ elements can be configured as different memories for forming memory subsystem.