Abstract: An ensemble learning based image classification system contains multiple cellular neural networks (CNN) based integrated circuits (ICs) operatively coupling together as a set of base learners of an ensemble for an image classification task. Each CNN based IC is configured with at least one distinct deep learning model in form of filter coefficients. The ensemble learning based image classification system further contains a controller configured as a meta learner of the ensemble and a memory based data buffer for holding various data used in the ensemble by the controller and the CNN based ICs. Various data may include input imagery data to be classified. Various data may also include extracted feature vectors or image classification outputs out of the set of base learners. The extracted feature vectors or image classification outputs are then used by the meta learner to further perform the image classification task.

Abstract: A system for encoding data in an artificial intelligence (AI) integrated circuit solution may include a processor configured to receive image/voice data and generate a sequence of two-dimensional (2D) arrays each array being shifted from a preceding 2D array in the sequence by a time difference. The system may load the sequence of arrays into an AI integrated circuit, feed each of the 2D arrays in the sequence into a respective channel in an embedded cellular neural network architecture in the AI integrated circuit. The system may generate an image/voice recognition result from the embedded cellular neural network architecture and output the image/voice recognition result. The sequence of 2D arrays in the image recognition may include a sequence of output images. The sequence of 2D arrays in the voice recognition may include 2D frequency-time arrays. Sample data may be encoded in a similar manner for training the cellular neural network.

Abstract: Methods of encoding image data for loading into an artificial intelligence (AI) integrated circuit are provided. The AI integrated circuit may have an embedded cellular neural network for implementing AI tasks based on the loaded image data. An encoding method may apply image splitting, principal component analysis (PCA) or a combination thereof to an input image to generate a plurality of output images. Each output image has a size smaller than the size of the input image. The method may load the output images into the AI chip, execute programming instructions contained in the AI chip to generate an image recognition result based on the at least one of the plurality of output images, and output the image recognition result. The encoding method also trains a convolution neural network (CNN) and loads the weights of the CNN into the AI integrated circuit for implementing the AI tasks.

Abstract: Two-dimensional symbols with each containing multiple ideograms for facilitating machine learning are disclosed. Two-dimensional symbol comprises a matrix of N×N pixels of data representing a “super-character”. The matrix is divided into M×M sub-matrices with each of the sub-matrices containing (N/M)×(N/M) pixels. N and M are positive integers or whole numbers, and N is preferably a multiple of M. Each of the sub-matrices represents one ideogram defined in an ideogram collection set. “Super-character” represents at least one meaning each formed with a specific combination of a plurality of ideograms. Ideogram collection set includes, but is not limited to, pictograms, logosyllabic characters, Japanese characters, Korean characters, punctuation marks, numerals, special characters. Logosyllabic characters may contain one or more of Chinese characters, Japanese characters, Korean characters. Features of each ideogram can be represented by more than one layer of two-dimensional symbol.

Abstract: A system may include a decentralized communication network and multiple processing devices on the network. Each processing device may have an artificial intelligence (AI) chip, the device may be configured to generate an AI model, determine the performance value of the AI model on the AI chip, receive a chain from the network where the chain contains a performance measure. If the performance value of the AI model is better than the performance measure, then the processing device may broadcast the AI model to the network for verification. If the AI model is verified by the network, the device may update the chain with the performance value so that the chain can be shared by the multiple processing devices on the network. Any processing device on the network may also verify an AI model broadcasted by any other device. Methods for generating the AI model are also provided.

Abstract: A system may include a decentralized communication network and multiple processing devices on the network. Each processing device may have an artificial intelligence (AI) chip, the device may be configured to generate an AI model, determine the performance value of the AI model on the AI chip, receive a chain from the network where the chain contains a performance measure. If the performance value of the AI model is better than the performance measure, then the processing device may broadcast the AI model to the network for verification. If the AI model is verified by the network, the device may update the chain with the performance value so that the chain can be shared by the multiple processing devices on the network. Any processing device on the network may also verify an AI model broadcasted by any other device. Methods for generating the AI model are also provided.

Abstract: A local processing device contains a bus, an input interface and at least one cellular neural networks (CNN) based integrated circuit (IC). The input interface is receiving a 2-D symbol representing a Chinese poetry or verse. The 2-D symbol is a matrix of N×N pixels of K-bit data that contains a “super-character”. The matrix is divided into M×M sub-matrices each containing (N/M)×(N/M) pixels. Each of the sub-matrices represents an ideogram. K, N and M are positive integers, and N is a multiple of M. CNN based IC is configured for understanding semantic meaning of the Chinese poetry or verse within the “super-character” contained in the 2-D symbol. The ideogram is created by embedded fonts of all of the characters contained in a corresponding phrase of the Chinese poetry or verse or is a pictogram representing artistic conception of each sentence of the Chinese poetry or verse.

Abstract: Image classification system contains a CNN based IC configured for extracting features out of input data by performing convolution operations using filter coefficients of ordered convolutional layers and a classifier IC configured for classifying the input data using reduced set of the extracted features based on a light-weight classifier. Light-weight classifier is derived by: training filter coefficients of the ordered convolutional layers using a dataset containing N labeled data, the trained filter coefficients are for the CNN based IC; outputting respective extracted features of the N labeled data after performing convolution operations of ordered convolutional layers using the trained filter coefficients, each labeled data contains X features; creating the reduced set of the extracted features by eliminating those of the X features that contain zeros in at least M of the N labeled data; and adjusting M until the light-weight classifier achieves satisfactory results using the reduced set.

Abstract: An integrated circuit includes an artificial intelligence (AID) logic and an embedded memory coupled to the AID logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.

Abstract: A deep learning object detection and recognition system contains a number of cellular neural networks (CNN) based integrated circuits (ICs) operatively coupling together via the network bus. The system is configured for detecting and then recognizing one or more objects out of a two-dimensional (2-D) imagery data. The 2-D imagery data is divided into N set of distinct sub-regions in accordance with respective N partition schemes. CNN based ICs are dynamically allocated for extracting features out of each sub-region for detecting and then recognizing an object potentially contained therein. Any two of the N sets of sub-regions overlap each other. N is a positive integer. Object detection is achieved with a two-category classification using a deep learning model based on approximated fully-connected layers, while object recognition is performed using a local database storing feature vectors of known objects.

Abstract: An ensemble learning based image classification system contains multiple cellular neural networks (CNN) based integrated circuits (ICs) operatively coupling together as a set of base learners of an ensemble for an image classification task. Each CNN based IC is configured with at least one distinct deep learning model in form of filter coefficients. The ensemble learning based image classification system further contains a controller configured as a meta learner of the ensemble and a memory based data buffer for holding various data used in the ensemble by the controller and the CNN based ICs. Various data may include input imagery data to be classified. Various data may also include extracted feature vectors or image classification outputs out of the set of base learners. The extracted feature vectors or image classification outputs are then used by the meta learner to further perform the image classification task.

Abstract: Multiple 3×3 convolutional filter kernels are used for approximating operations of fully-connected (FC) layers. Image classification task is entirely performed within a CNN based integrated circuit. Output at the end of ordered convolutional layers contains P feature maps with F×F pixels of data per feature map. 3×3 filter kernels comprises L layers with each organized in an array of R×Q of 3×3 filter kernels, Q and R are respective numbers of input and output feature maps of a particular layer of the L layers. Each input feature map of the particular layer comprises F×F pixels of data with one-pixel padding added around its perimeter. Each output feature map of the particular layer comprises (F?2)×(F?2) pixels of useful data. Output of the last layer of the L layers contains Z classes. L equals to (F?1)/2 if F is an odd number. P, F, Q, R and Z are positive integers.

Abstract: CNN based integrated circuit is configured with a set of pre-trained filter coefficients or weights as a feature extractor of an input data. Multiple fully-connected networks (FCNs) are trained for use in a hierarchical category classification scheme. Each FCN is capable of classifying the input data via the extracted features in a specific level of the hierarchical category classification scheme. First, a root level FCN is used for classifying the input data among a set of top level categories. Then, a relevant next level FCN is used in conjunction with the same extracted features for further classifying the input data among a set of subcategories to the most probable category identified using the previous level FCN. Hierarchical category classification scheme continues for further detailed subcategories if desired.

Abstract: Method and systems of replacing operations of depthwise separable filters with first and second replacement convolutional layers are disclosed. Depthwise separable filters contains a combination of a depthwise convolutional layer followed by a pointwise convolutional layer with input of P feature maps and output of Q feature maps. The first replacement convolutional layer contains P×P of 3×3 filter kernels formed by placing each of the P×1 of 3×3 filter kernels of the depthwise convolutional layer on respective P diagonal locations, and zero-value 3×3 filter kernels zero-value 3×3 filter kernels in all off-diagonal locations. The second replacement convolutional layer contains Q×P of 3×3 filter kernels formed by placing Q×P of 1×1 filter coefficients of the pointwise convolutional layer in center position of the respective Q×P of 3×3 filter kernels, and numerical value zero in eight perimeter positions.

Abstract: Methods of encoding voice data for loading into an artificial intelligence (AI) integrated circuit are provided. The AI integrated circuit may have an embedded cellular neural network for implementing AI tasks based on the loaded voice data. An encoding method may generate a two-dimensional (2D) frequency-time array from an audio waveform, use the 2D frequency-time array to generate a set of 2D arrays to approximate the 2D frequency-time array, load the set of 2D arrays into the AI integrated circuit, execute programming instructions contained in the AI integrated circuit to feed the set of 2D arrays into the embedded cellular neural network in the AI integrated circuit to generate a voice recognition result, and output the voice recognition result. The encoding method also trains a convolution neural network (CNN) and loads the weights of the CNN into the AI integrated circuit for implementing the AI tasks.

Abstract: An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.

Abstract: Operations of a combination of first and second original convolutional layers followed by a short path are replaced by operations of a set of three particular convolutional layers. The first contains 2N×N filter kernels formed by placing said N×N filter kernels of the first original convolutional layer in left side and N×N filter kernels of an identity-value convolutional layer in right side. The second contains 2N×2N filter kernels formed by placing the N×N filter kernels of the second original convolutional layer in upper left corner, N×N filter kernels of an identity-value convolutional layer in lower right corner, and N×N filter kernels of two zero-value convolutional layers in either off-diagonal corner. The third contains N×2N of kernels formed by placing N×N filter kernels of a first identity-value convolutional layer and N×N filter kernels of a second identity-value convolutional layer in a vertical stack. Each filter kernel contains 3×3 filter coefficients.

Abstract: An artificial intelligence inference computing device contains a printed circuit board (PCB) and a number of electronic components mounted thereon. Electronic components include a wireless communication module, a controller module, a memory module, a storage module and at least one cellular neural networks (CNN) based integrated circuit (IC) configured for performing convolutional operations in a deep learning model for extracting features out of input data. Each CNN based IC includes a number of CNN processing engines operatively coupled to at least one input/output data bus. CNN processing engines are connected in a loop with a clock-skew circuit. Wireless communication module is configured for transmitting pre-trained filter coefficients of the deep learning model, input data and classification results.

Abstract: Embedded memory subsystems in a digital integrated circuit for artificial intelligence are disclosed. A semi-conductor substrate contains CNN processing units. Each CNN processing unit includes CNN logic circuits and an embedded memory subsystem. The memory subsystem includes first memory and second memory. The first memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area with a diameter in a range of 40-120 nm. The second memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area having a diameter in a range of 30-75 nm.

Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory includes an array of magnetic random access memory (RAM) cells for storing weights (e.g., filter coefficients) and the second memory contains SRAM for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains magnetic RAM cells for storing one-time-programming data for security purpose. The magnetic RAM includes STT-RAM or OST-MRAM in SLC or MLC technology.