Abstract: A three-dimensional processor (3D-processor) for parallel computing includes a plurality of computing elements. Each computing element comprises at least a three-dimensional memory (3D-M) array for storing at least a portion of a look-up table (LUT) for a mathematical function and an arithmetic logic circuit (ALC) for performing arithmetic operations on the LUT data. Deficiency in latency is offset by a large scale of parallelism.

Abstract: A discrete three-dimensional (3-D) processor a plurality of storage-processing units (SPU's), each of which comprises a non-memory circuit and more than one 3-D memory (3D-M) array. The preferred 3-D processor further comprises communicatively coupled first and second dice. The first die comprises the 3D-M arrays and the in-die peripheral-circuit components thereof; whereas, the second die comprises the non-memory circuits and off-die peripheral-circuit components of the 3D-M arrays.

Abstract: A discrete three-dimensional (3-D) processor comprises a plurality of storage-processing units (SPU's), each of the SPU's comprising a non-memory circuit, at least a memory array and at least an off-die peripheral-circuit component thereof. The 3-D processor further comprises first and second dice. The first die comprises the memory arrays, whereas the second die comprises the non-memory circuit and the off-die peripheral-circuit component.

Abstract: A discrete three-dimensional (3-D) processor comprises communicatively coupled first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises at least a non-memory circuit and at least an off-die peripheral-circuit component of the 3D-M arrays. The first die does not comprise said off-die peripheral-circuit component. The non-memory circuit on the second die is not part of a memory.

Abstract: A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays and in-die peripheral-circuit components thereof, whereas the second die comprises processing circuits and off-die peripheral-circuit components of the 3D-M arrays. The first and second dice are communicatively coupled by a plurality of inter-die connections.

Abstract: A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D random-access memory or 3-D read-only memory (3D-RAM/3D-ROM) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-RAM/3D-ROM arrays. The first die does not comprise the off-die peripheral-circuit component of the 3D-RAM/3D-ROM arrays.

Abstract: A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). Typical off-die peripheral-circuit component could be an address decoder, a sense amplifier, a programming circuit, a read-voltage generator, a write-voltage generator, a data buffer, or a portion thereof.

Abstract: A discrete three-dimensional (3-D) processor comprises communicatively coupled first and second dice. The first die comprises memory arrays, whereas the second die comprises at least a non-memory circuit and at least an off-die peripheral-circuit component of the memory arrays. The first and second dice have substantially different structures, more particularly back-end-of-line (BEOL) structures.

Abstract: A discrete three-dimensional (3-D) processor comprises stacked first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). In one preferred embodiment, the first and second dice are vertically stacked. In another preferred embodiment, the first and second dice are face-to-face bonded.

Abstract: A discrete three-dimensional (3-D) processor a plurality of storage-processing units (SPU's), each of which comprises a non-memory circuit and more than one 3-D memory (3D-M) array. The preferred 3-D processor further comprises communicatively coupled first and second dice. The first die comprises the 3D-M arrays and the in-die peripheral-circuit components thereof; whereas, the second die comprises the non-memory circuits and off-die peripheral-circuit components of the 3D-M arrays.

Abstract: A discrete three-dimensional (3-D) processor comprises communicatively coupled first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises at least a non-memory circuit and at least an off-die peripheral-circuit component of the 3D-M arrays. The first die does not comprise said off-die peripheral-circuit component. The non-memory circuit on the second die is not part of a memory.

Abstract: A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D random-access memory (3D-RAM) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-RAM arrays. The first die does not comprise the off-die peripheral-circuit component of the 3D-RAM arrays.

Abstract: A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). Typical off-die peripheral-circuit component could be an address decoder, a sense amplifier, a programming circuit, a read-voltage generator, a write-voltage generator, a data buffer, or a portion thereof.

Abstract: A discrete three-dimensional (3-D) processor comprises stacked first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). In one preferred embodiment, the first and second dice are face-to-face bonded. In another preferred embodiment, the first and second dice have a same die size.

Abstract: A discrete three-dimensional (3-D) processor comprises stacked first and second dice. The first die comprises three-dimensional memory (3D-M) arrays, whereas the second die comprises at least a portion of a logic/processing circuit and an off-die peripheral-circuit component of the 3D-M array(s). The preferred 3-D processor can be used to compute non-arithmetic function/model. In other applications, the preferred 3-D processor may also be a 3-D configurable computing array, a 3-D pattern processor, or a 3-D neuro-processor.

Abstract: A discrete 3-D processor comprises first and second dice. The first die comprises three-dimensional memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network.

Abstract: A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network.

Abstract: A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays and in-die peripheral-circuit components thereof, whereas the second die comprises processing circuits and off-die peripheral-circuit components of the 3D-M arrays. The first and second dice are communicatively coupled by a plurality of inter-die connections.

Abstract: A manufacturing method of a three-dimensional vertical memory (3D-MV) includes the steps of: (A) forming a stack of interleaved lightly-doped layers and insulating layers; and, (B) a first photolithography step and an ion-implant step to form first and second regions in each lightly-doped layer. The first region, disposed around and shared by a plurality of memory holes, has a higher resistivity than the second region.

Abstract: A configurable processor doublet comprises a pair of face-to-face bonded three-dimensional memory (3D-M) die and processing die. The 3D-M die comprises 3D-M arrays, whereas the processing die comprises arithmetic-logic circuits (ALC's). The preferred doublet also comprises an array of configurable computing elements (CCE's). Each CCE comprises at least a 3D-M array, an ALC, and inter-storage-processor (ISP) connections.