Abstract: A configurable processor singlet is a single die comprising monolithically integrated three-dimensional memory (3D-M) arrays and arithmetic-logic circuits (ALC's). The preferred singlet also comprises an array of configurable computing elements (CCE's). Each CCE comprises at least a 3D-M array, an ALC, and inter-storage-processor (ISP) connections.
Type:
Grant
Filed:
October 8, 2020
Date of Patent:
September 21, 2021
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A three-dimensional processor (3D-processor) for calculating mathematical functions in parallel, comprises a larger number (e.g. at least one thousand) of computing elements, with each computing element comprising at least one three-dimensional memory (3D-M) array for storing at least a portion of a look-up table (LUT) for a mathematical function and an arithmetic logic circuit (ALC) for performing arithmetic operations on the LUT data. Even though each individual 3D-M cell is slower than a conventional two-dimensional memory (2D-M) cell, this deficiency in speed is offset by a significantly larger scale of parallelism.
Type:
Grant
Filed:
June 30, 2019
Date of Patent:
August 3, 2021
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A neuro-processor comprises a plurality of neural storage-processing units (NSPU's). Each NSPU comprises a neuro-storage circuit and a neuro-processing circuit. The neuro-processing circuit comprises a multiplier disposed on a semiconductor substrate and a three-dimensional memory (3D-M) array stacked above the multiplier. The 3D-M array stores at least a portion of a look-up table (LUT) of an activation function and at least partially overlaps the multiplier.
Type:
Application
Filed:
April 11, 2021
Publication date:
July 29, 2021
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: The present invention discloses an integrated neuro-processor comprising at least a three-dimensional memory (3D-M) array. The 3D-M array stores the synaptic weights, while the neuro-processing circuit performs neural processing. The 3-D integration between the 3D-M array and the neuro-processing circuit not only improves the computational power per die area, but also greatly increases the storage capacity per die area.
Type:
Grant
Filed:
March 21, 2017
Date of Patent:
July 20, 2021
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A GaN-on-Si output transistor array comprises a plurality of small monolithic output transistors. Multiple pieces of the small monolithic GaN films are grown epitaxially on the silicon substrate. Each small monolithic output transistor is formed in a respective small monolithic GaN film. The normal transistors are connected in serial, while the defective transistors are not connected.
Type:
Grant
Filed:
May 25, 2020
Date of Patent:
July 6, 2021
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A vertically integrated neuro-processor comprises a plurality of neural storage-processing units (NSPU's). Each NSPU comprises at least a neuro-storage circuit and a neuro-processing circuit. The neuro-storage circuit comprises a memory array for storing at least a synaptic weight, while the neuro-processing circuit performs neural processing with the synaptic weight. The memory array and the neuro-processing circuit are vertically stacked and communicatively coupled by a plurality of inter-level connections.
Type:
Grant
Filed:
January 16, 2019
Date of Patent:
July 6, 2021
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A manufacturing method of a three-dimensional vertical memory (3D-MV) includes the steps of: (A) forming a stack of interleaved lightly-doped layers and insulating layers; and, (B) a first photolithography step and an ion-implant step to form first and second regions in each lightly-doped layer. The first region, disposed around and shared by a plurality of memory holes, has a higher resistivity than the second region.
Type:
Application
Filed:
January 24, 2021
Publication date:
May 13, 2021
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A configurable processor singlet is a single die comprising monolithically integrated three-dimensional memory (3D-M) arrays and arithmetic-logic circuits (ALC's). The preferred singlet also comprises an array of configurable computing elements (CCE's). Each CCE comprises at least a 3D-M array, an ALC, and inter-storage-processor (ISP) connections.
Type:
Application
Filed:
October 8, 2020
Publication date:
March 18, 2021
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A configurable processor doublet comprises a pair of face-to-face bonded three-dimensional memory (3D-M) die and processing die. The 3D-M die comprises 3D-M arrays, whereas the processing die comprises arithmetic-logic circuits (ALC's). The preferred doublet also comprises an array of configurable computing elements (CCE's). Each CCE comprises at least a 3D-M array, an ALC, and inter-storage-processor (ISP) connections.
Type:
Application
Filed:
October 8, 2020
Publication date:
March 18, 2021
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network.
Type:
Application
Filed:
November 15, 2020
Publication date:
March 18, 2021
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: In a shared three-dimensional vertical memory (3D-MV), each horizontal address line comprises at least two regions: a lightly-doped region and a low-resistivity region. The lightly-doped region is formed around selected memory holes and shared by a plurality of low-leakage memory cells. The low-resistivity region forms a conductive network to reduce the resistance of the horizontal address line.
Type:
Grant
Filed:
November 22, 2019
Date of Patent:
March 2, 2021
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A configurable processor comprises at least an array of configurable computing elements (CCE's). Each CCE comprises at least a three-dimensional (3-D) memory (3D-M) array; an arithmetic logic circuit (ALC); and, a plurality of inter-storage-processor (ISP) connections. Not penetrating through any semiconductor substrate, the ISP-connections are short, small and numerous.
Type:
Grant
Filed:
November 24, 2019
Date of Patent:
November 24, 2020
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A three-dimensional processor (3D-processor) for parallel computing includes a plurality of computing elements. Each computing element comprises at least a three-dimensional memory (3D-M) array for storing at least a portion of a look-up table (LUT) for a mathematical function and an arithmetic logic circuit (ALC) for performing arithmetic operations on the LUT data. Deficiency in latency is offset by a large scale of parallelism.
Type:
Application
Filed:
July 26, 2020
Publication date:
November 12, 2020
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A GaN-on-Si output transistor array comprises a plurality of small monolithic output transistors. Multiple pieces of the small monolithic GaN films are grown epitaxially on the silicon substrate. Each small monolithic output transistor is formed in a respective small monolithic GaN film. The normal transistors are connected in serial, while the defective transistors are not connected.
Type:
Application
Filed:
May 25, 2020
Publication date:
September 10, 2020
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: The present invention discloses a processor comprising three-dimensional memory (3D-M) array (3D-processor). Instead of logic-based computation (LBC), the 3D-processor uses memory-based computation (MBC). It comprises an array of computing elements, with each computing element comprising an arithmetic logic circuit (ALC) and a 3D-M-based look-up table (3DM-LUT). The ALC performs arithmetic operations on the LUT data, while the 3DM-LUT is stored in at least one 3D-M array.
Type:
Grant
Filed:
April 13, 2017
Date of Patent:
September 1, 2020
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: To detect front-parked vehicles at night (i.e. a vehicle is parked with its head facing the inside of a parking space), a detection device uses the light beam from a passing-by vehicle to extract at least a reflection of at least a tail light or at least a portion of a back bumper from an image captured for a parking space.
Type:
Grant
Filed:
September 8, 2019
Date of Patent:
August 11, 2020
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A bi-sided pattern processor comprises a plurality of storage-processing units (SPU's). Each of the SPU's comprises at least a memory array and a pattern-processing circuit. The preferred pattern processor further comprises a semiconductor substrate with opposing first and second surfaces. The memory array is disposed on the first surface, whereas the pattern-processing circuit is disposed on the second surface. The memory array stores patterns; the pattern-processing circuit processes these patterns; and, they are communicatively coupled by a plurality of inter-surface connections.
Type:
Grant
Filed:
January 16, 2019
Date of Patent:
July 14, 2020
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A GaN-on-Si output transistor array comprises a plurality of small monolithic output transistors. The substrate surface has multiple grids, upon which multiple pieces of the small monolithic GaN films are grown epitaxially on the silicon substrate. Each small monolithic output transistor is formed in a respective small monolithic GaN film. By disabling defective transistors, the overall yield/reliability is improved.
Type:
Grant
Filed:
December 24, 2018
Date of Patent:
July 7, 2020
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A positioning method using music pieces continuously provides positioning service. At each signature burst (i.e., a highly unique short musical segment suitable for positioning), sounds of a music piece are used for positioning. Between signature bursts, dead reckoning (DR) is used.
Type:
Grant
Filed:
August 7, 2018
Date of Patent:
July 7, 2020
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A double-biased three-dimensional one-time-programmable read-only memory (3D-OTP) comprises an OTP array stacked on a semiconductor substrate. The OTP array comprises a dummy word line, a plurality of data word lines and data bit lines. The dummy OTP cells at the intersections of the dummy word line and all data bit lines are unprogrammed. During read, both voltages on the dummy word line and a selected data word line are raised.
Type:
Grant
Filed:
September 9, 2018
Date of Patent:
July 7, 2020
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.