Abstract: Instead of logic-based computation (LBC), the preferred processor disclosed in the present invention uses memory-based computation (MBC). It comprises an array of computing elements, with each computing element comprising a memory array on a memory level for storing a look-up table (LUT) and an arithmetic logic circuit (ALC) on a logic level for performing arithmetic operations on selected LUT data. The memory level and the logic level are different physical levels.
Type:
Application
Filed:
November 12, 2018
Publication date:
April 18, 2019
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A preferred configurable computing-array package comprises a configurable logic die including an array of configurable logic elements and a configurable computing die including an array of configurable computing elements. Each configurable logic element is capable of realizing any one of a plurality of logic functions in a logic library. Each configurable computing element stores at least a look-up table (LUT) for a math function, which includes more operations than the arithmetic operations included in the logic library.
Type:
Application
Filed:
November 25, 2018
Publication date:
April 18, 2019
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A configurable computing-array package comprises a configurable computing die including an array of configurable computing elements and a configurable logic die including an array of configurable logic elements. Each configurable computing element stores a look-up table (LUT) for a non-arithmetic function, i.e. a math function whose operations involve more than addition and subtraction. The configurable computing-array package can be configured to realize different complex math functions.
Type:
Application
Filed:
November 24, 2018
Publication date:
April 18, 2019
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: The present invention discloses a configurable gate array comprising three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a basic function in a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the basic functions in the math library.
Type:
Grant
Filed:
March 13, 2018
Date of Patent:
March 12, 2019
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: Manufacturing methods of JFET-type compact three-dimensional memory (3D-MC) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A JFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.
Type:
Grant
Filed:
March 9, 2017
Date of Patent:
February 19, 2019
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: The present invention discloses a configurable computing array based on three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a basic function in a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the basic functions in the math library.
Type:
Grant
Filed:
March 19, 2018
Date of Patent:
February 19, 2019
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: Manufacturing methods of MOSFET-type compact three-dimensional memory (3D-MC) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A MOSFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.
Type:
Grant
Filed:
March 8, 2017
Date of Patent:
February 5, 2019
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A positioning method using music pieces continuously provides positioning service. At each signature burst (i.e., a highly unique short musical segment suitable for positioning), sounds of a music piece are used for positioning. Between signature bursts, dead reckoning (DR) is used.
Type:
Application
Filed:
August 7, 2018
Publication date:
December 20, 2018
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: To implement a complex math function, a configurable computing array comprises at least an array of configurable interconnects, an array of configurable logic elements and an array of configurable computing elements. Each configurable computing element comprises at least a memory for storing a look-up table (LUT) for a math function.
Type:
Application
Filed:
August 8, 2018
Publication date:
December 20, 2018
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: To implement a math function with multiple input variables, a configurable computing array comprises at least an array of configurable interconnects, an array of configurable logic elements, and an array of configurable computing elements. Each configurable computing element comprises at least a memory for storing a look-up table (LUT) for a math function with a single input variable.
Type:
Application
Filed:
August 6, 2018
Publication date:
December 13, 2018
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: The present invention discloses a new type of configurable gate array—a configurable computing array die based on two-sided integration. It is a monolithic die and comprises at least a configurable computing element and a configurable logic element formed on different sides of a semiconductor substrate. Each configurable computing element can selectively realize a basic function from a math library. It comprises a plurality of printed arrays for storing the look-up tables (LUT) for different basic functions.
Type:
Grant
Filed:
March 9, 2018
Date of Patent:
December 4, 2018
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: The present invention discloses a multi-bit-per-cell three-dimensional read-only memory (3D-OTPMB) comprising a plurality of dummy bit lines. It comprises a plurality of OTP cells stacked above a semiconductor substrate. Each OTP array comprises at least four dummy bit lines.
Type:
Application
Filed:
August 7, 2018
Publication date:
November 29, 2018
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: To detect front-parked vehicles at night (i.e. a vehicle is parked with its head facing the inside of a parking space), a detection device uses the light beam from a passing-by vehicle to extract at least a reflection of at least a tail light or at least a portion of a back bumper from an image captured for a parking space.
Type:
Application
Filed:
August 7, 2018
Publication date:
November 29, 2018
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A positioning method using music pieces continuously provides positioning service. At each signature burst (i.e., a highly unique short musical segment suitable for positioning), sounds of a music piece are used for positioning. Between signature bursts, dead reckoning (DR) is used.
Type:
Application
Filed:
July 26, 2018
Publication date:
November 15, 2018
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: To detect front-parked vehicles at night (i.e. a vehicle is parked with its head facing the inside of a parking space), the present invention discloses a night-detection device. It comprises a moving-vehicle sensor and a parked-vehicle sensor. It uses the light beam from a passing-by vehicle to extract at least a reflection of at least a tail light or at least a portion of a back bumper.
Type:
Application
Filed:
July 25, 2018
Publication date:
November 15, 2018
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A preferred IR-bicycle comprises an infrared (IR) sensor and non-IR electronics. The IR sensor detects a person in the proximity of the IR-bicycle (i.e. a nearby person). Once the IR sensor detects a nearby person, the non-IR electronics switches from a first mode to a second mode, wherein the power consumption in the first mode is substantially lower than that in the second mode.
Type:
Application
Filed:
April 29, 2018
Publication date:
November 1, 2018
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: The present invention discloses a configurable gate array based on three-dimensional writable memory (3D-W). It comprises an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which is electrically programmable and can be loaded with a look-up table (LUT) for a math function.
Type:
Grant
Filed:
October 13, 2017
Date of Patent:
October 30, 2018
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: Music-based positioning (MP) provides positioning service only sporadically. To continuously provide positioning service, the present invention discloses music-based positioning aided by dead reckoning (MP-DR). At each signature burst (i.e., a highly unique short musical segment suitable for positioning), sounds of a music piece or a human speech are used for positioning. Between signature bursts, dead reckoning (DR) is used.
Type:
Grant
Filed:
December 18, 2016
Date of Patent:
September 25, 2018
Assignees:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A preferred image-recognition processor comprises a plurality of storage-processing units (SPU), with each SPU comprising at least a three-dimensional memory (3D-M) array vertically stacked above a pattern-processing circuit. The 3D-M array stores at least a portion of an image model from an image model database. The image data from the input are sent to all SPUs, which perform pattern recognition simultaneously.
Type:
Application
Filed:
May 20, 2018
Publication date:
September 20, 2018
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.
Abstract: A preferred processor for enhancing network security comprises a plurality of storage-processing units (SPU), with each SPU comprising at least a three-dimensional vertical one-time-programmable memory (3D-OTPV) array vertically stacked above a pattern-processing circuit. The 3D-OTPV array stores at least a portion of rule/malware database. An incoming network packet from the input is sent to all SPUs, which perform rule enforcement and/or anti-malware operation simultaneously.
Type:
Application
Filed:
May 24, 2018
Publication date:
September 20, 2018
Applicant:
HangZhou HaiCun Information Technology Co., Ltd.