Patents Assigned to HangZhou HaiCun Information Technology Co., Ltd
  • Compact three-dimensional mask-programmed read-only memory
    Patent number: 10079239
    Abstract: A compact three-dimensional mask-programmed read-only memory (3D-MPROMC) is disclosed. Its memory array and a decoding stage thereof are formed on a same memory level above the substrate. The memory layers of the memory devices in the memory array have at least two different thicknesses, while the middle layer of the decoding device in the decoding stage has the same thickness as the thinnest memory layer.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: September 18, 2018
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Audio Storage with In-Situ Audio-Searching Capabilities
    Publication number: 20180260477
    Abstract: A preferred audio storage with in-situ audio-searching capabilities not only stores audio data, but also performs pattern recognition thereto. It comprises a plurality of storage-processing units (SPU), with each SPU comprising at least a three-dimensional memory (3D-M) array vertically stacked above a pattern-processing circuit. The 3D-M array stores at least a portion of audio data, while the input includes at least a portion of an audio pattern.
    Type: Application
    Filed: May 8, 2018
    Publication date: September 13, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Distributed Pattern Storage-Processing Circuit Comprising Three-Dimensional Memory Arrays
    Publication number: 20180260449
    Abstract: A distributed pattern storage-processing circuit not only stores patterns permanently, but also processes them with massive parallelism. It comprises a plurality of storage-processing units (SPU), with each SPU comprising at least a three-dimensional memory (3D-M) array vertically stacked above a pattern-processing circuit. The plurality of SPUs performs pattern processing simultaneously.
    Type: Application
    Filed: May 8, 2018
    Publication date: September 13, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Speech-Recognition Processor
    Publication number: 20180261226
    Abstract: A preferred speech-recognition processor performs pattern processing (i.e. pattern recognition) between an acoustic/language model and an audio data. It comprises a plurality of storage-processing units (SPU), with each SPU comprising at least a three-dimensional memory (3D-M) array vertically stacked above a pattern-processing circuit. The plurality of SPUs can perform pattern processing simultaneously.
    Type: Application
    Filed: May 8, 2018
    Publication date: September 13, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Distributed Pattern Storage-Processing Circuit Comprising Three-Dimensional Vertical Memory Arrays
    Publication number: 20180260344
    Abstract: The present invention discloses a distributed pattern storage-processing circuit. It not only stores patterns permanently, but also processes them with massive parallelism. The preferred pattern storage-processing circuit comprises a plurality of storage-processing units (SPU), with each SPU comprising at least a three-dimensional memory (3D-M) array vertically stacked above a pattern-processing circuit. The plurality of SPUs performs pattern processing simultaneously.
    Type: Application
    Filed: May 7, 2018
    Publication date: September 13, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Data Storage with In-situ String-Searching Capabilities Comprising Three-Dimensional Vertical Memory Arrays
    Publication number: 20180260644
    Abstract: A preferred data storage with in-situ string-searching capabilities comprises a plurality of storage-processing units (SPU), with each SPU comprising at least a three-dimensional vertical memory (3D-MV) array vertically stacked above a pattern-processing circuit. The 3D-MV array stores at least a portion of big data. A search string from the input is sent to all SPUs, which perform string searching simultaneously.
    Type: Application
    Filed: May 9, 2018
    Publication date: September 13, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Three-Dimensional Vertical Multiple-Time-Programmable Memory Comprising Multiple Re-programmable Sub-Layers
    Publication number: 20180204845
    Abstract: The present invention discloses a three-dimensional vertical multiple-time-programmable memory (3D-MTPV). It comprises horizontal address lines and memory holes there-through, a re-programmable layer and vertical address lines in said memory holes. The re-programmable layer comprises at least first and second sub-layers with different re-programmable materials. The 3D-MTPV comprises no separate diode layer.
    Type: Application
    Filed: March 13, 2018
    Publication date: July 19, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Configurable Computing Array Package Based on Printed Memory
    Publication number: 20180198449
    Abstract: The present invention discloses a new type of configurable gate array—a configurable computing array package. It comprises at least a configurable computing die and a configurable logic die. The configurable computing die comprises at least one configurable computing element. The configurable computing element can selectively realize a basic function from a math library. It comprises a plurality of printed arrays for storing the look-up tables (LUT) for different basic functions. The configurable computing die and the configurable logic die are located in a same package.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Configurable Computing Array Die Based on Printed Memory and Two-Sided Integration
    Publication number: 20180198448
    Abstract: The present invention discloses a new type of configurable gate array—a configurable computing array die based on two-sided integration. It is a monolithic die and comprises at least a configurable computing element and a configurable logic element formed on different sides of a semiconductor substrate. Each configurable computing element can selectively realize a basic function from a math library. It comprises a plurality of printed arrays for storing the look-up tables (LUT) for different basic functions.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Offset-printing method for three-dimensional printed memory with multiple bits-per-cell
    Patent number: 9990960
    Abstract: The present invention discloses an offset-printing method for a three-dimensional printed memory with multiple bits-per-cell. The mask-patterns for different bits-in-a-cell are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different bits-in-a-cell.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 5, 2018
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Offset-printing method for three-dimensional printed memory
    Patent number: 9959910
    Abstract: The present invention discloses an offset-printing method for a three-dimensional printed memory. The mask-patterns for different memory levels are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different memory levels.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: May 1, 2018
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Configurable gate array based on three-dimensional printed memory
    Patent number: 9948306
    Abstract: The present invention discloses a configurable gate array based on three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a math function from a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the math functions in the math library.
    Type: Grant
    Filed: March 5, 2017
    Date of Patent: April 17, 2018
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Configurable gate array based on three-dimensional writable memory
    Patent number: 9838021
    Abstract: The present invention discloses a configurable gate array based on three-dimensional writable memory (3D-W). It comprises an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which is electrically programmable and can be loaded with a look-up table (LUT) for a math function.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: December 5, 2017
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Integrated Neuro-Processor Comprising Three-Dimensional Memory Array
    Publication number: 20170270403
    Abstract: The present invention discloses an integrated neuro-processor comprising at least a three-dimensional memory (3D-M) array. The 3D-M array stores the synaptic weights, while the neuro-processing circuit performs neural processing. The 3-D integration between the 3D-M array and the neuro-processing circuit not only improves the computational power per die area, but also greatly increases the storage capacity per die area.
    Type: Application
    Filed: March 21, 2017
    Publication date: September 21, 2017
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Configurable Gate Array Based on Three-Dimensional Printed Memory
    Publication number: 20170257100
    Abstract: The present invention discloses a configurable gate array based on three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a math function from a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the math functions in the math library.
    Type: Application
    Filed: March 5, 2017
    Publication date: September 7, 2017
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Configurable Gate Array Based on Three-Dimensional Writable Memory
    Publication number: 20170257101
    Abstract: The present invention discloses a configurable gate array based on three-dimensional printed memory (3D-W). It comprises an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which is electrically programmable and can be loaded with a look-up table (LUT) for a math function.
    Type: Application
    Filed: March 6, 2017
    Publication date: September 7, 2017
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Distributed Pattern Processor Comprising Three-Dimensional Memory Array
    Publication number: 20170255834
    Abstract: The present invention discloses a distributed pattern processor. The distributed pattern processor not only stores patterns permanently, but also processes them using massive parallelism. It comprises a plurality of storage-processing units (SPU), with each SPU comprising a pattern-processing circuit and at least a three-dimensional memory (3D-M) array storing at least a pattern. The 3D-M array is vertically stacked above the pattern-processing circuit.
    Type: Application
    Filed: March 7, 2017
    Publication date: September 7, 2017
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Three-dimensional 3D-oP-based package
    Patent number: 9741697
    Abstract: The present invention discloses a three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package (3D2-oP). The mask-patterns for different dice in a same 3D2-oP package are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different dice in a same 3D2-oP package.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: August 22, 2017
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Processor Comprising Three-Dimensional Memory (3D-M) Array
    Publication number: 20170237440
    Abstract: The present invention discloses a processor comprising three-dimensional memory (3D-M) array (3D-processor). Instead of logic-based computation (LBC), the 3D-processor uses memory-based computation (MBC). It comprises an array of computing elements, with each computing element comprising an arithmetic logic circuit (ALC) and a 3D-M-based look-up table (3DM-LUT). The ALC performs arithmetic operations on the LUT data, while the 3DM-LUT is stored in at least one 3D-M array.
    Type: Application
    Filed: April 13, 2017
    Publication date: August 17, 2017
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao ZHANG, Chen SHEN
  • Mixed Three-Dimensional Memory
    Publication number: 20170229158
    Abstract: The present invention discloses a mixed three-dimensional memory (3D-Mx). Both data and codes are stored in a same 3D-Mx die. Data, which require a lower cost per bit and can tolerate slow access, are stored in large memory arrays, whereas codes, which require fast access and can tolerate a higher cost per bit, are stored in small memory arrays.
    Type: Application
    Filed: April 23, 2017
    Publication date: August 10, 2017
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG