Abstract: A receiver apparatus can identify a plurality of patterns corresponding to scrambled synchronization bytes of a transport stream in a number of successive signal frames containing FEC code blocks, determine a pattern distribution into which most of the patterns identified in the successive signal frames map, and generate a synchronization signal locked to a distribution of the FEC code blocks associated with the pattern distribution. With this synchronization signal, FEC code blocks can be timely handled in a reliable manner through a FEC decoder, making the receiver apparatus more efficient and robust. In other embodiments, methods of handling FEC code blocks in a receiver apparatus are also described.

Abstract: A broadcast receiver includes a tuner circuit and a demodulator circuit. The tuner circuit tunes a radio frequency (RF) signal to output an intermediate frequency (IF) signal. The demodulator circuit demodulates the IF signal from the tuner circuit and outputs a command signal based on the quality of the IF signal, for changing a take over point (TOP) value, preset in the tuner circuit, at which one amplitude gain control (AGC) stopping and another taking over. A method for regulating a broadcast receiver is also disclosed herein.

Abstract: A pattern-dependent error correction method and system for a code group alignment finite state machine (FSM) are disclosed. A state corrector generates a start-of-stream delimiter (SSD) detected signal to the FSM when the FSM is in an idle state and at least one condition due to a lost SSD signal is met; and the state corrector generates an idle detected signal to the FSM when at least one condition due to a lost idle signal is met. A pattern corrector generates a corrected code pattern {J,K} to FSM when the FSM is in an idle state and at least one condition due to a false idle state is met; and the pattern corrector generates a corrected code pattern {T,R} to the FSM when the FSM is in a data state, a start of stream state or a data error state, and at least one condition due to a false packet end is met.

Abstract: An apparatus for generating sine/cosine values of an input phase is disclosed. The apparatus includes a phase projector, an LUT-arithmetic unit, a temp sine/cosine generator and a sine/cosine value generator. The phase projector maps the input phase angle into an octant phase and determines an octant index indicating which octant the input phase angle actually locates and a flag indicating whether or not the input phase happens to be pi/4, 3*pi/4, 5*pi/4 or 7*pi/4. The LUT-arithmetic unit receives the octant phase for provision of its corresponding sine/cosine values. The temp sine/cosine generator receives the corresponding sine/cosine values of the octant phase for provision of temp sine/cosine values based on the flag. The sine/cosine value generator selectively swaps and inverts the temp sine/cosine values as the sine/cosine values of the input phase based on a swap index derived from the octant index.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window.

Abstract: The present invention is directed to a recoverable Ethernet receiver. A joint decision feedback equalizer (DFE) and Trellis decoder is configured to decode a receiving signal to result in a received symbol, and configured to generate a check-idle value which is used to indicate an idle mode. A physical coding sublayer (PCS) block is configured to generate a seed value and a polarity characterization according to the received symbol, with the joint DFE and Trellis decoder generating the check-idle value according to the seed value and the polarity characterization.

Abstract: An adaptive Ethernet transceiver is disclosed. A joint decision feedback equalizer (DFE) and Trellis decoder is configured to decode a receiving signal. A decoder control unit is configured to adaptively disable a portion of the joint DFE and Trellis decoder in a non-specified link speed mode.

Abstract: The present invention is directed to joint decision feedback equalizer (DFE) and Trellis decoder adaptable to an Ethernet transceiver. A Trellis coded modulation (TCM) decoder includes a one-dimensional branch metric unit (1D-BMU) configured to calculate 1D branch metrics; a four-dimensional branch metric unit (4D-BMU) configured to combine the 1D branch metrics to generate 4D branch metrics; an add-compare-select unit (ACSU) configured to perform add, compare and select (ACS) operations on the 4D branch metrics for each state to obtain path metrics; and a survivor memory unit (SMU) configured to store and keep track of symbols. A decision feedback unit (DFU) is coupled to receive the symbols from the SMU in order to estimate inter-symbol interference (ISI) quantity, which is then fed back to the 1D-BMU.

Abstract: The present invention provides a method and apparatus of controlling an operational status of an electronic device which receives data through a HDMI port. The present invention determines whether to wake up the electronic device from the power saving mode according to counting numbers generated based on the transitions of signals within a time period.

Abstract: A method for frame rate up conversion. The method is executed by a frame rate up-converter. The frame rate up-converter receives a plurality of consecutive input video frames and detects luminance information for a current frame. The frame rate up-converter generates a first output frame according to the luminance information for the current frame and a preceding frame before the current frame and generates a second output frame according to the luminance information for the current frame and a succeeding frame after the current frame, wherein the second output frame is outputted after the first output frame.

Abstract: A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a predefined frame code is determined. The beginning and the end of the clock window are then adaptively determined based on the falling edge and the time difference, such that symbol timing recovery through received clock run-in signals may be performed within the generated clock window.

Abstract: A backlight control system and method are disclosed. An overdrive device modifies a backlight duty signal according to a current-frame backlight duty signal and a previous-frame backlight duty signal. In one embodiment, the overdrive device is implemented with a lookup table that outputs the modified backlight duty signal. The backlight driven by the modified backlight duty signal then emits light to a display panel, thereby increasing a response time of the backlight.

Abstract: An adaptive color-temperature calibration system and method are disclosed. A chrominance generation unit generates a chrominance criterion according to an input pixel. A matrix generation unit generates a calibration matrix according to the chrominance criterion and a basis matrix. A color calibration unit then performs color-temperature calibration on the input pixel according to the generated calibration matrix, thereby generating an output pixel.

Abstract: The present disclosure provides a method for adjusting 3-D images converted from 2-D images by using a human visual model. Steps of the method include inputting a 2-D image, dividing the 2-D image into a plurality of blocks, forming a matrix of blocks, obtaining a depth value of each of the plurality of blocks, adjusting the depth value of each of the plurality of blocks according to a position of each of the plurality of blocks, obtaining adjusted depth information of the 2-D image, wherein the adjusted depth information comprises an adjusted depth value of each of the plurality of blocks of the 2-D image, and using depth image based rendering (DIBR) to generate a set of 3-D images according to the adjusted depth information and the 2-D image.

Abstract: The invention is directed to a stereo image correction system and method. A shift unit vertically shifts one image of a stereo image pair with a shifted amount, and a depth generator generates a depth map of the shifted image pair. A high-pass filter processes the depth map to result in a filtered output, and an analysis unit determines a matching point according to the filtered outputs and the corresponding shifted amounts, wherein the shifted amount at the matching point is determined as a matched shifted amount. A compensation unit vertically shifts the image to be shifted of the stereo image pair with the matched shifted amount.

Abstract: In a method of block-based motion estimation a motion vector map is obtained by obtaining a motion vector of each macroblock (MB) in the current frame with respect to the reference frame. The motion vector of each MB in an interpolated frame is then determined according to the motion vector map.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window.

Abstract: A depth map generating device. A first depth information extractor extracts a first depth information from a main two dimensional (2D) image according to a first algorithm and generates a first depth map corresponding to the main 2D image. A second depth information extractor extracts a second depth information from a sub 2D image according to a second algorithm and generates a second depth map corresponding to the sub 2D image. A mixer mixes the first depth map and the second depth map according to adjustable weighting factors to generate a mixed depth map. The mixed depth map is utilized for converting the main 2D image to a set of three dimensional (3D) images.

Abstract: A backlight controller, a display device using the same and a method for controlling a backlight module are provided. The backlight controller includes a temporal weighting module and a dimming controlling module. The temporal weighting module calculates a weight sum of a first backlight luminance provided in a current frame and a target backlight luminance to serve as an adjusted backlight luminance. The target backlight luminance is obtained according to an image content of the current frame. The dimming controlling module increases or decreases the adjusted backlight luminance by a step value according to the target backlight luminance and generates a second backlight luminance provided in a next frame. Therefore, a backlight luminance of the backlight module not only can be smoothly adjusted to the target backlight luminance at high speed for avoiding backlight flicker, but also can be adaptive to image content for saving electric power consumption.

Abstract: The invention discloses a digital demodulating apparatus for timing error detection, including a numerically controlled oscillator, an equalizer unit, a decoder and a timing error detector. The numerically controlled oscillator generates a first sequence signal according to an input sequence signal and a timing error sequence signal. The equalizer unit equalizes the first sequence signal to generate an equalized sequence signal. The decoder decodes the equalized sequence signal to generate to generate an output sequence signal. The timing error detector generates the timing error sequence signal according to the first sequence signal and one of the equalized sequence signal and the output sequence signal.