Abstract: A sample hold circuit and a method for sampling and holding a signal are provided. The sample hold circuit includes a sample unit, a direct current (DC) voltage elimination unit, and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an input signal, and the DC voltage elimination unit lowers a predetermined percentage of the DC voltage in the input signal sampled by the sample unit. When the sample hold circuit is in a second state, the DC voltage elimination unit eliminates the residual percentage of the DC voltage, and the hold unit outputs the alternating current (AC) signal in the input signal sampled by the sample unit.

Abstract: A standby circuit and method for a display device is disclosed. A detector detects voltage drop of the first termination resistor of a positive path of a clock channel, and the second termination resistors of a negative path. Upon detecting the voltage drop, a switch controller disconnects the positive path or the negative path that has the detected voltage drop, thereby saving power in the standby mode of the display device.

Abstract: An adaptive color-temperature calibration system and method are disclosed. A chrominance generation unit generates a chrominance criterion according to an input pixel. A matrix generation unit generates a calibration matrix according to the chrominance criterion and a basis matrix. A color calibration unit then performs color-temperature calibration on the input pixel according to the generated calibration matrix, thereby generating an output pixel.

Abstract: The invention is directed to a frame rate up conversion (FRUC) system and method. A motion estimation (ME) unit is configured to generate at least one motion vector (MV) according to a frame input. A triple-line buffer based motion compensation (MC) unit is configured to generate an interpolated frame according to the MV, a reference frame and a current frame, thereby generating a frame output with a frame rate higher than a frame rate of the frame input.

Abstract: In a method of occlusion handling, a reference frame and a current frame are first provided, and at least one foreground object is determined. At least a covered region or an uncovered region with respect to the foreground object is determined. The covered region is then interpolated exclusively accordingly to the current frame, or the uncovered region is interpolated exclusively according to the reference frame.

Abstract: In a method of block-based motion estimation a motion vector map is obtained by obtaining a motion vector of each macroblock (MB) in the current frame with respect to the reference frame. The motion vector of each MB in an interpolated frame is then determined according to the motion vector map.

Abstract: An image enhancement apparatus is provided. The image enhancement apparatus includes a global tone mapping curve generator, a local tone mapping curve generator, a reference gamma voltage generator and an image generator. The global tone mapping curve generator generates a global tone mapping curve for an input image according to global characteristic(s) of the input image. The local tone mapping curve generator generates a local tone mapping curve for each image partition within the input image according to the global tone mapping curve and further a feature of the image partition. The reference gamma voltage generator generates a plurality of reference gamma voltages for each image partition according to the corresponding local tone mapping curve for the image partition. The image generator generates an output image according to the reference gamma voltages of the image partitions and the input image.

Abstract: A system and method for generating test patterns of baseline wander, such as worst-case test patterns commonly referred to as killer packets. The number of steps required to cycle an output of a multi-level encoder in order to arrive at an anticipated level is determined. A test packet generator then generates the test patterns according to the determined steps and the state of a scrambler.

Abstract: A content-adaptive overdrive system and method, for a display panel, include a frame difference device and an overdrive device. The frame difference device generates a frame difference map according to a current frame and a previous frame. The frame difference map includes a number of flags respectively indicating similarity between corresponding pixels or blocks of the current frame and the previous frame. The overdrive device adaptively performs an overdrive function based on the frame difference map, the current frame, the previous frame and an overdrive lookup table, hence resulting in an overdrived frame.

Abstract: A system and method for generating test patterns of baseline wander, such as worst-case test patterns commonly referred to as killer packets. The number of steps required to cycle an output of a multi-level encoder in order to arrive at an anticipated level is determined. A test packet generator then generates the test patterns according to the determined steps and the state of a scrambler.

Abstract: One embodiment of the present invention sets forth a method of generating a packet identifier table that comprises reading a packet identifier value from a received transport stream packet, identifying a type of data contained in the received transport stream packet, and generating a table with mapping information between the packet identifier value and the identified type of data.

Abstract: An automatic gain control apparatus includes a first comparing module, a counting module, a second comparing module, and a control module. The first comparing module compares an input signal with a first threshold level and a second threshold level to generate a first compared output signal and a second compared output signal respectively. The counting module performs counting operations upon the first compared output signal and the second compared output signal to generate a first counting number and a second counting number respectively. The second comparing module compares the first counting number with a first threshold number to generate a first detection signal and compares the second counting number with a second threshold number to generate a second detection signal. The control module controls the gain of a radio frequency amplifier or an intermediate frequency amplifier according to the first detection signal and the second detection signal.

Abstract: An analog-to-digital conversion unit (ADC unit) and an analog-to-digital converting method (ADC method) are provided. The ADC unit has a plurality of sub analog-to-digital converters and an encoding unit. Each of the employed sub analog-to-digital converters is coupled to two threshold voltages non-successive in terms of levels arrangement, compares the input voltage with the two threshold voltages and outputs two bits according to the comparison results. In this way, the difference between the two threshold voltages coupled by each of the sub analog-to-digital converters can be larger, which is advantageous in advancing the analog-to-digital converting accuracy.

Abstract: A method for adjusting the volume of a digital audio signal includes detecting a level in accordance with an audio input signal, determining a gain value in accordance with the detected level, and outputting an audio output signal in accordance with the gain value and the audio input signal. Accordingly, weak audio signals such as background noise in silent periods may be compressed to reduce interference to the human listening experience during such silent periods.

Abstract: A binary arithmetic decoding device may include a first and second lookup table each receive signal output from a first register. A third lookup table receives signal output from the first lookup table and a fourth lookup table receives signal output from the second lookup table. A first multiplexer receives signal output from the third and fourth lookup tables. A second multiplexer receives signal output from the first and second lookup tables and from the second lookup table where the first and second multiplexers are controlled by a same first signal. The proposed decoder may further include a second register, a first adder, a third adder, and a first comparison module coupled in series and output of the first comparison module is the first signal.

Abstract: A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a predefined frame code is determined. The beginning and the end of the clock window are then adaptively determined based on the falling edge and the time difference, such that symbol timing recovery through received clock run-in signals may be performed within the generated clock window.

Abstract: A sample hold circuit and a method for eliminating the offset voltage of the analog signal are provided. The sample hold circuit includes a sample unit, a plurality of capacitors, a control unit and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an analog signal. When the sample hold circuit is in a second state, the capacitors eliminate a DC offset voltage of the analog signal sampled by the sample unit, and the hold unit outputs an AC signal of the analog signal sampled by the sample unit. The control unit adjusts a number of the capacitances coupled to a common voltage according to a magnitude of the DC offset voltage, thus to determine the capacitance for eliminating the DC offset voltage.

Abstract: A sample hold circuit and a method for eliminating the offset voltage of the analog signal are provided. The sample hold circuit includes a sample unit, a plurality of capacitors, a control unit and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an analog signal. When the sample hold circuit is in a second state, the capacitors eliminate a DC offset voltage of the analog signal sampled by the sample unit, and the hold unit outputs an AC signal of the analog signal sampled by the sample unit. The control unit adjusts a number of the capacitances coupled to a common voltage according to a magnitude of the DC offset voltage, thus to determine the capacitance for eliminating the DC offset voltage.

Abstract: A sample hold circuit and a method for sampling and holding a signal are provided. The sample hold circuit includes a sample unit, a direct current (DC) voltage elimination unit, and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an input signal, and the DC voltage elimination unit lowers a predetermined percentage of the DC voltage in the input signal sampled by the sample unit. When the sample hold circuit is in a second state, the DC voltage elimination unit eliminates the residual percentage of the DC voltage, and the hold unit outputs the alternating current (AC) signal in the input signal sampled by the sample unit.

Abstract: An analog-to-digital conversion unit (ADC unit) and an analog-to-digital converting method (ADC method) are provided. The ADC unit has a plurality of sub analog-to-digital converters and an encoding unit. Each of the employed sub analog-to-digital converters is coupled to two threshold voltages non-successive in terms of levels arrangement, compares the input voltage with the two threshold voltages and outputs two bits according to the comparison results. In this way, the difference between the two threshold voltages coupled by each of the sub analog-to-digital converters can be larger, which is advantageous in advancing the analog-to-digital converting accuracy.