Abstract: A video processing apparatus. A first scaling module receives original images according to an original pixel clock and performs adjustments on the original images according to a first scaling ratio to generate first scaled images. A frame buffer buffers the first scaled images. A controller controls the frame buffer to receive the first scaled images according to a first pixel clock and output the first scaled images according to a second pixel clock. A second scaling module receives the first scaled images and performs adjustments on the first scaled images according to a second scaling ratio to generate second scaled images. A length of a vertical blanking interval of the second scaled images is longer than a length of a vertical blanking interval of the original images.

Abstract: An ISI removing method for a received signal executed by a receiver in an OFDM system to estimate a frequency-domain data signal carried on the received signal is provided. The method comprises the steps of: removing the first interference of known signal of the received signal; estimating a first data signal according to the received signal; performing a hard decision operation on the first data signal to generate a first frequency-domain signal; performing an Inverse Fast Fourier Transform operation on the first frequency-domain signal to generate a first time-domain signal; creating a tailing signal according to the first time-domain signal; removing a preamble signal from the received signal to generate a second signal; combining the first time-domain signal and the second signal to estimate the frequency-domain data signal.

Abstract: A receiver with capability of correcting error is disclosed. A soft slicer generates quantized data and associated soft data. A decoder with error recovery generates decoded quantized data and a soft sequence, and is capable of correcting one bit of the quantized data. A serial-to-parallel (S/P) converter with code corrector generates parallel data, and is capable of correcting two bits of de-scrambled data bits.

Abstract: An image enhancement apparatus is provided. The image enhancement apparatus includes a global tone mapping curve generator, a local tone mapping curve generator, a reference gamma voltage generator and an image generator. The global tone mapping curve generator generates a global tone mapping curve for an input image according to global characteristic(s) of the input image. The local tone mapping curve generator generates a local tone mapping curve for each image partition within the input image according to the global tone mapping curve and further a feature of the image partition. The reference gamma voltage generator generates a plurality of reference gamma voltages for each image partition according to the corresponding local tone mapping curve for the image partition. The image generator generates an output image according to the reference gamma voltages of the image partitions and the input image.

Abstract: A memory access system and method for efficiently utilizing memory bandwidth is disclosed. A data arrangement unit arranges video data into at least a primary block and a supplemental block, which are then stored in a memory device. The video data are arranged such that the video data of the primary block stored in the memory device can be sequentially read by a device, thereby increasing efficiency in memory bandwidth usage and memory data access.

Abstract: A channel estimation method for use with a received signal by a receiver is disclosed. The received signal comprises multiple data bursts which are transmitted to the receiver via multiple path channels, with each of the data bursts having a plurality of preamble symbols which are decoded. The channel estimation method includes the following steps: firstly, at least one correlation pattern is generated according to the decoded preamble symbols. Then, a cross correlation of the correlation pattern with the received signal is performed to yield at least one correlation result of channel impulse response (CIR). Wherein, the symbol boundary of the received signal is decided according to the correlation result.

Abstract: A method and system of receiving data with enhanced partial matching is disclosed. A received word is compared with the frame code to determine mismatch bit(s). Subsequently, a determination is made whether the mismatch bit(s) are at positions of defined critical bits. If the mismatch bit(s) are not critical, the received word is then affirmed.

Abstract: A multi-format video decoder includes a bitstream buffer, a system controller, a bitstream decoding unit, an intra mode decoding unit and a shared prediction module. The system controller selectively generates a first control signal or a second control signal according to a video bitstream. The bitstream decoding unit generates a decoding information signal according to the video bitstream when receiving the first control signal. The intra mode decoding unit generates an intra mode signal when receiving the second control signal. The shared prediction module performs an AC/DC prediction upon a current block of the video bitstream to generate a current first prediction result according to the decoding information signal and performs an intra prediction upon the current block to generate a current second prediction result according to the intra mode signal. The shared prediction module includes shared components being utilized in the AC/DC prediction and the intra prediction.

Abstract: A video horizontal synchronizer outputting a line timing signal and an indicating flag of a received video signal for use in a video signal post-processing unit, including a filter outputting a wide bandwidth filtered and a narrow bandwidth filtered signals of the received video signal, a dynamic slicer threshold generator generating a slicer threshold, a timing recovery circuit generating a phase error and the line timing signal, a phase error statistics circuit averaging the phase error to generate a average phase error, a HSYNC checker generating a matching flag indicating whether a periodic pattern appears in the narrow bandwidth filtered signal according to the line timing signal, and a finite state machine controlling the dynamic slicer threshold generator, the timing recovery circuit, the phase error statistics circuit and the HSYNC checker and generating an indicating flag when the average phase error is small enough and the matching flag is confirmed.

Abstract: A stereo image displaying method adapted to a polarizing panel is provided. The stereo image displaying method includes the following steps. An original first eye image and the original second eye image are received. Each of the odd pixel data rows of the original first eye image is interpolation operated with at least one of two adjacent even pixel data rows of original the first eye image to serve as one of a plurality of pixel data rows of a first eye image of a display frame. Each of the even pixel data rows of the original second eye image is interpolation operated with at least one of two adjacent odd pixel data rows of the original second eye image to serve as one of a plurality of pixel data rows of a second eye image of the display frame. The display frame is applied on the polarizing panel.

Abstract: A pattern-dependent error correction method and system for a code group alignment finite state machine (FSM) are disclosed. A state corrector generates a start-of-stream delimiter (SSD) detected signal to the FSM when the FSM is in an idle state and at least one condition due to a lost SSD signal is met; and the state corrector generates an idle detected signal to the FSM when at least one condition due to a lost idle signal is met. A pattern corrector generates a corrected code pattern {J,K} to FSM when the FSM is in an idle state and at least one condition due to a false idle state is met; and the pattern corrector generates a corrected code pattern {T,R} to the FSM when the FSM is in a data state, a start of stream state or a data error state, and at least one condition due to a false packet end is met.

Abstract: Frame data stored in an external memory is partitioned into a plurality of macroblocks, and a plurality of access units each comprising at least one macroblock are provided. A plurality of frames are fetched from the external memory by loading the plurality of access units in a predetermined sequence. A current data for decoding a macroblock of the first access unit and a reference data for decoding a macroblock of the second access unit are loaded from the first access unit, and respectively mapped to a first memory group and a second memory group of a circular cache according to the frame width.

Abstract: A system and method of contrast enhancement is disclosed. A contrast enhancement unit processes an input pixel to generate a contrast-enhanced pixel, and a delta unit subtracts the input pixel from the contrast-enhanced pixel, thereby resulting in a difference value. Multiple delayed difference values generated by a delay unit are low-pass filtered to generate a refined difference value. An adding unit adds back the refined difference value to the input pixel, thereby resulting in an output pixel that is contrast-enhanced without noise boost.

Abstract: A video standard detector and operation method thereof are provided. The video standard detector includes a low pass filter (LPF) unit and a standard detector unit. The LPF filters a baseband signal. The feature detector detects vertical synchronization information of the baseband signal and horizontal synchronization information of the baseband signal using the output of the LPF, and determines the video standard corresponding to the baseband signal according to the vertical synchronization information and the horizontal synchronization information.

Abstract: A 2D-to-3D color compensation method for compensating color processing in a display device is disclosed. The display device is coupled with a 2D-to-3D conversion box. The method includes the following steps: firstly, the 2D-to-3D conversion box sends out a combined calibration pattern to the display device. Then, the display device performs image processing for the combined calibration pattern. Subsequently, detect a difference value between the combined calibration pattern processed by the display device and the original combined calibration pattern. Finally, adjust the combined calibration pattern according to the difference value.

Abstract: A bit-stream buffer controller for a video decoder includes a first FIFO, a second FIFO, and an interrupt controller. The first FIFO is configured to store an input bit-stream. The second FIFO is configured to store a payload extracted from the input bit-stream. The interrupt controller is configured to generate an interrupt signal according to a fullness status of the first FIFO and the second FIFO such that the video decoder may be switched to load the payload without checking the fullness status each time the payload is loaded.

Abstract: A tap/group-revivable decision feedback equalizing method and equalizer using the same is disclosed. The equalizer includes a feed-forward filter and a feedback filter each with a plurality of taps divided in groups. The tap/group-revivable decision equalizing method includes training all the taps to generate their tap coefficients, and selecting all the taps of any of the groups with a tap coefficient greater than a predetermined value and selecting a number of taps of any of the groups without a tap coefficient greater than the predetermined value, but with a neighboring group with a tap coefficient greater than the predetermined value are selected, and having the selected taps utilized for equalization.

Abstract: A 2D-to-3D delay compensation method for making a pair of shutter glasses be synchronization with a display device's playback of a video source is disclosed. The display device is coupled with a 2D-to-3D conversion box. The method includes the following steps: firstly, the 2D-to-3D conversion box sends out a calibration pattern to the display device. Then, a shutter control signal is sent out after waiting a delay time to switch on and off the left and right lenses of the pair of shutter glasses. Subsequently, the calibration pattern is detected. Finally, determine whether the delay time must be adjusted or not according to the detecting result.

Abstract: A source driving circuit includes a gamma voltage generator, a common voltage generator and a driver. The gamma voltage generator receives gamma data from a timing controller through reduced swing differential signaling (RSDS) transmission interface to generate corresponding gamma voltages. The common voltage generator receives common voltage data from the timing controller to generate a corresponding common voltage. The driver receives image data from the timing controller through the RSDS transmission interface, the gamma voltages from the gamma voltage generator and the common voltage from the common voltage generator for modifying the image data using the gamma voltages and the common voltage and transmitting the modified image data to a panel of the liquid crystal display.

Abstract: A sound-IF demodulator including a first demodulating unit and a second demodulating unit and a sound-IF detecting method thereof are provided. A sound de-matrix unit is adapted to generate a driving signal by de-matrixing outputs of the sound-IF demodulator. The first demodulating unit generates a first demodulated signal to the sound de-matrix unit by demodulating the first carrier signal. The second demodulating unit detects the signal quality of the sound signal and generates a second demodulated signal to the sound de-matrix unit and/or the first demodulating unit by demodulating the second carrier signal. When the second demodulating unit is idle, the second demodulating unit is programmed to select a corresponding standard among a plurality of predetermined standards for the sound signal according to the signal quality of the sound signal, so that the sound-IF demodulator is programmed to demodulate the sound signal in the corresponding standard.