Abstract: A parallel based 5 bypass bin CABAC decoder may include a 3 bypass bins decoder appropriately coupled to a 2 bypass bins decoder. The 3 bypass bins decoder may have a first input receiving a bitstream, a second input receiving range values, a first output outputting a first bypass bin, a second output outputting a second bypass bin, a third output outputting a third bypass bin, and a fourth output outputting a shifted bitstream to the 2 bypass bins decoder. The 2 bypass bins decoder may have a first input to receive the shifted bitstream, a second input to receive the range values, a first output outputting a fourth bypass bin, and a second output outputting a fifth bypass bin.

Abstract: A display device including a remote control unit and a display panel unit is provided. The display panel unit includes a plurality of optical receivers and a track recognizer. The remote control unit emits a light beam. The optical receivers receive the light beam and convert the light beam into a plurality of sensing voltages. The track recognizer generates a control command according to the sensing voltages so that the display panel unit sets an on-screen display (OSD).

Abstract: A method and system of receiving data with enhanced partial matching is disclosed. A received word is compared with the frame code to determine mismatch bit(s). Subsequently, a determination is made whether the mismatch bit(s) are at positions of defined critical bits. If the mismatch bit(s) are not critical, the received word is then affirmed.

Abstract: A voltage regulator and an integrated circuit using the voltage regulator is provided. The voltage regulator has a bandgap reference circuit, an operational amplifier, a power transistor and a voltage divider. The bandgap reference circuit generates a bandgap reference voltage. The operational amplifier receives the bandgap reference voltage and a feedback voltage to output a control signal for the power transistor. The power transistor is powered by a first voltage source and transforms the first voltage source to a second voltage source according to the control signal. The second voltage source is divided by the voltage divider to generate the feedback voltage and is further used in powering the bandgap reference circuit and the operational amplifier.

Abstract: An image enhancement apparatus is provided. The image enhancement apparatus includes a global contrast curve generator, a local contrast curve generator and an image generator. The global contrast curve generator generates a global contrast curve for an input image according to a global histogram of the input image. The local contrast curve generator generates a local contrast curve for each image partition within the input image according to the global contrast curve and further a feature of the image partition. The image generator generates an output image by enhancing a contrast of each image partition according to the local contrast curve for the image partition and the input image, and merging the enhanced image partitions.

Abstract: An analog-to-digital conversion circuit is provided. A voltage divider of the analog-to-digital conversion circuit regulates a voltage range received by a sample holder of analog-to-digital conversion circuit. Accordingly, a first half of the sample holder can use an electrical device with a low operating voltage. Since an operation speed of the electrical device with the low voltage is faster than an electrical device with a high operating voltage, an operation frequency of the sample holder can be raised.

Abstract: A video horizontal synchronizer outputting a line timing signal and an indicating flag of a received video signal for use in a video signal post-processing unit, including a filter outputting a wide bandwidth filtered and a narrow bandwidth filtered signals of the received video signal, a dynamic slicer threshold generator generating a slicer threshold, a timing recovery circuit generating a phase error and the line timing signal, a phase error statistics circuit averaging the phase error to generate a average phase error, a HSYNC checker generating a matching flag indicating whether a periodic pattern appears in the narrow bandwidth filtered signal according to the line timing signal, and a finite state machine controlling the dynamic slicer threshold generator, the timing recovery circuit, the phase error statistics circuit and the HSYNC checker and generating an indicating flag when the average phase error is small enough and the matching flag is confirmed.

Abstract: An analog-to-digital converter (ADC) for pipelined ADCs or cyclic ADCs is disclosed. The ADC includes at least one pair of two stages connected in series, and the two stages have different bits of resolution. An amplifier is shared by the pair of two stages such that the two stages operate in an interleaved manner. Accordingly, this stage-resolution scalable opamp-sharing technique is adaptable for pipelined ADC or cyclic ADC, which substantially reduces power consumption and increases operating speed.

Abstract: A system and method of contrast enhancement is disclosed. A contrast enhancement unit processes an input pixel to generate a contrast-enhanced pixel, and a delta unit subtracts the input pixel from the contrast-enhanced pixel, thereby resulting in a difference value. Multiple delayed difference values generated by a delay unit are low-pass filtered to generate a refined difference value. An adding unit adds back the refined difference value to the input pixel, thereby resulting in an output pixel that is contrast-enhanced without noise boost.

Abstract: An audio output device is provided and includes a power source, a controller, a signal generating circuit, and a first amplifier. The power source provides a supply voltage signal. The controller receives the supply voltage signal. The controller further compares the supply voltage signal with a threshold voltage signal and generates a control signal according to the comparison result. The signal generating circuit generates a first analog signal. The first amplifier receives the first analog signal and generates a first amplified signal according to the control signal.

Abstract: An audio output device is provided and includes a signal source, a detector, a plurality of digital-to-analog converters, and a plurality of amplifiers. The signal source generates a plurality of digital signals. The detector receives the digital signals and detects states of the digital signals to generate a plurality of control signals according to the detection results respectively. The digital-to-analog converters receive the digital signals and convert the digital signals to a plurality of analog signals, respectively. The amplifiers receive the analog signals and generate a plurality of amplified signals according to the control signals, respectively.

Abstract: A data accessing system bridges a first master device and a second master device to a first slave device and a second slave device. The data accessing system includes a register, a first multiplexer, a second multiplexer and a control unit. The amount of data that the first master device can process each cycle is less than which of the second slave device. The data accessing system can solve the problem when the first master device writes data to the second slave device via merging two different data. Also, the data accessing system can solve the problem when the first master device reads data to the second slave device via extracting part of the data.

Abstract: A video standard detector and operation method thereof are provided. The video standard detector includes a low pass filter (LPF) unit and a standard detector unit. The LPF filters a baseband signal. The feature detector detects vertical synchronization information of the baseband signal and horizontal synchronization information of the baseband signal using the output of the LPF, and determines the video standard corresponding to the baseband signal according to the vertical synchronization information and the horizontal synchronization information.

Abstract: A sound-IF demodulator including a first demodulating unit and a second demodulating unit and a sound-IF detecting method thereof are provided. A sound de-matrix unit is adapted to generate a driving signal by de-matrixing outputs of the sound-IF demodulator. The first demodulating unit generates a first demodulated signal to the sound de-matrix unit by demodulating the first carrier signal. The second demodulating unit detects the signal quality of the sound signal and generates a second demodulated signal to the sound de-matrix unit and/or the first demodulating unit by demodulating the second carrier signal. When the second demodulating unit is idle, the second demodulating unit is programmed to select a corresponding standard among a plurality of predetermined standards for the sound signal according to the signal quality of the sound signal, so that the sound-IF demodulator is programmed to demodulate the sound signal in the corresponding standard.

Abstract: A method and system of automatically correcting a sampling clock in a digital video system are disclosed. Sampling clocks with different phases are generated and subjected in turn to analog-to-digital conversion (ADC). A difference of at least a pair of neighboring data out of the ADC with respect to each phase is determined. A maximum difference is determined, and the sampling clock with the phase corresponding to the maximum difference is thus generated.

Abstract: A method and system of receiving data with enhanced error correction is disclosed. One or more reliability bits associated with each received data bit are generated, for example, by a soft-decision slicer. Subsequently, one or more errors of the data bits may be corrected according to the associated reliability bit(s).

Abstract: A method for frame rate up conversion is provided. The method includes the steps of: receiving a plurality of consecutive input video frames; detecting luminance information for a current frame; and generating a first output frame according to the luminance information for the current frame and a preceding frame before the current frame and generating a second output frame according to the luminance information for the current frame and a succeeding frame after the current frame, wherein the second output frame is outputted after the first output frame.

Abstract: A method for color calibration is provided. The method includes the steps of: providing an input color; obtaining luminance of the input color; determining a grey level of the input color according to luminance of the input color; determining a first calibration matrix and a second calibration matrix according to the grey level of the input color; generating a third calibration matrix according to the first calibration matrix, the second calibration matrix and the grey level of the input color; generating an output color according to the third calibration matrix and the input color.

Abstract: An analog to digital converter is provided. The converter comprises a first stage, an adjustment unit and a digital error correction logic. The first stage has a first sensing range and receives a first voltage to generate a first digital code. The adjustment unit adjusts the first sensing range of the first stage. The digital error correction logic receives and corrects the first digital code to generate a digital code corresponding to the first voltage.

Abstract: The invention discloses a digital IF demodulator for processing a digital IF signal converted from a radio frequency (RF) signal, including an NCO, a down conversion circuit, a PIF carrier recovery circuit and a video baseband demodulator. The NCO outputs a sine value and a cosine value. The down conversion circuit outputs a first zero IF signal including a first real part signal and a first imaginary part signal, according to the digital IF signal, the sine value and the cosine value. The PIF carrier recovery circuit outputs a loop error signal for the NCO and a second zero IF signal, according to the first zero IF signal and a video synchronization signal. The video baseband demodulator generates a composite video signal according to the second zero IF signal.