Abstract: In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

Abstract: A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.

Abstract: In order to obtain a highly stable SRAM cell having a small cell area, a cell ratio R is set to be R=(W.sub.DEFF /L.sub.DEFF)/(W.sub.TEFF /L.sub.TEFF)<3 where L.sub.DEFF and W.sub.DEFF denote an effective channel length and an effective channel width of two driver MOSFETs 3 and 4 respectively, and L.sub.TEFF and W.sub.TEFF denote an effective channel length and an effective channel width of two transfer MOSFETs 5 and 6 respectively. Further, a maximum current I.sub.R flowing into the active loads MOSFETs 1 and 2 is set to be greater than a current I.sub.L (1.times.10.sup.-8 A) that flows into the driver MOSFET 5 when a threshold voltage is applied across the gate and the cource of the MOSFET 5. The pair of active load MOSFETs 1 and 2 are stacked on the driver MOSFETs 3 and 4 and on the transfer MOSFETs 5 and 6.

Abstract: A semiconductor memory device has a plurality of memory blocks, each block including a matrix arrangement of a plurality of nonvolatile memory elements. The device is also provided with at least one redundant data line which is selectively employed in place of a defective data line associated with a defective address in a memory block. The data lines corresponding to the respective memory blocks are selectively coupled to corresponding ones of first common data lines by a Y selector circuit in accordance with outputs of a first Y decoder, while a redundant data line is controllably coupled to a redundant common data line by a redundant selector circuit in accordance with an output of a redundant decoder.

Abstract: A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor.

Abstract: A data storage device for storing data strings each including units of data has a plurality of memory sections each for storing therein a table, a plurality of processor elements one provided for each of the tables and a controlling unit having an internal memory in which data strings are stored. The table contains a plurality of records each including a unit of data, a first index data representative of the number of units of data of a data string which the unit of data constitutes and a second index data unique to each individual data string. The processor elements access in parallel their associated tables under control of the control unit for data storage and data retrieval. The first and index data are generated by the controller for the purpose of data storage.

Abstract: According to the present invention, as improvement in the adhesion of inner leads with a packaging resin in a resin-sealed semiconductor device is attained by spreading leads on or near the circuit-forming face of a pellet, or on or near the main non-circuit-forming face of the pellet to extend the lengths of the inner leads on or under the pellet.

Abstract: A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed.

Abstract: Disclosed is a preferable method for producing an avalanche photo diode in which an impurity-doped region having a relatively high concentration and a step-like distribution has a step portion in another impurity-doped region having a relatively low concentration and a gradational distribution so that the circumferential portion of the high concentration region is made shallow in comparison with the central portion of the same, the step portion having a shape so that the radius of curvature thereof varies continuously.

Abstract: A voltage comparator is provided including a differential amplifier, first, second and third switches, and first and second capacitors. A fourth switch is connected in series between the second and third switches and an input terminal of the differential amplifier. A first input voltage is sampled and held at the first capacitor through the first switch and at the second capacitor through the second and fourth switches, respectively. Thereafter, since the third switch is turned on and the fourth switch is turned off, the first input voltage is sampled and held at the input capacitor of the differential amplifier. Thereafter, the third switch is turned off and the fourth switch turned on. As a result, an on and off operation of the fourth switch is controlled so that a second input voltage which has been sampled at the second capacitor immediately before the switch is turned off is applied to the input capacitor of the differential amplifier.

Abstract: A signal transmission circuit in which a signal is converted into two complementary signals which are outputted from a signal transmission circuit via series resistors. The amplitude of each of the complimentary signals is reduced by the series resistors and terminating resistors provided on a signal receiving side. The signal receiving side shifts the level of the signals which it inputs. The level shifted signals are amplified by a high-input impedance differential amplifying circuit.

Abstract: A semiconductor device of pin-grid array (PGA) type, which is adapted for surface-mounting on a printed circuit board, has lead pins arranged in a grid and standing perpendicularly on a base of the semiconductor device. In addition, a few pins are provided which are longer than said lead pins in said grid. When the device is placed on the printed circuit board for mounting, the longer pins are inserted into through-holes which are respectively formed in the printed circuit board to correspond to the position of the longer pins of the device. Thus, the tip of the lead pins are accurately positioned on the top of lands on the printed circuit board, respectively, and the lead pins do not get out of position during the mounting operation.

Abstract: Means for changing-over address signals is provided in an address input portion, and the order of the signals to be input to an address decoder is changed according to external control signals. Alternatively, a reading output circuit is provided which reads data in bit unit different from that of the writing input circuit. Thus, data can be read and written even when the number of bits of data differs between in case of accessing a built-in memory of an LSI inside the LSI and in case of accessing it from outside the LSI.

Abstract: A time circuit is provided for a nonvolatile memory device which can electrically be written into. When the write operation on a particular memory cell lasting a relatively long period of time is specified from an external device, the memory device stops the write operation on that memory cell, irrespective of the external write operaiton specification, when the time set on the timer circuit has elapsed. The nonvolatile memory device has memory cells, each consisting of a single transistor. The erase operation on the memory cells is controlled according to a current flowing through these memory cells.

Abstract: An invention relating to a technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, and more particularly pertaining to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.

Abstract: A processing apparatus includes a processing chamber and an insertion jig for inserting an object to be processed into the processing chamber. The processing chamber and the insertion jig are adapted to be individually movable relative to a heating section, so that the operation of loading and unloading the object into and from the processing chamber effected by the insertion jig is conducted outside the heating section, thereby preventing the outside air from being induced to enter the heated processing chamber, together with the object of the processing, and thus avoiding the occurrence of various problems, for example, the object of processing being disorderly oxidized by the oxygen contained in the outside air, and the foreign matter contained in the outside air being undesirably attached to the surface of the object, so as to obtain excellent processing results.

Abstract: Attempts have been made to increase the number of pins of packages accompanying the trend toward fabricating integrated circuits highly densely and in smaller sizes. The present invention provides technology for improving reliability in fabricating packages of the surface-mounted type that have increased number of pins. That is, when the packages are mounted on the wiring substrate, the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength of solder at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as a fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material.

Abstract: Each memory cell of the memory array has a latch circuit, such as a pair of cross-connected CMOS inverters, for storing information, a first switch MOSFET whose gate is connected with a word line, and a second switch MOSFET which is connected in series with the first switch MOSFET and the gate of which is connected with the output terminal of the latch circuit. The first and second switch MOSFETs are coupled between the data line and a terminal supplied with a first power source voltage level, such as reference ground potential. Such memory cells are disposed at intersections of a plurality of data lines and a plurality of word lines. One of the plurality of data lines is connected with a common data line through a column switch which is alternatively brought into an ON state.

Abstract: In the semiconductor integrated circuit device provided with a plurality of second well regions of the same conductivity type, formed by dividing a first well region provided in the semiconductor substrate by an isolation trench, the isolation trench is substantially linear on the semiconductor substrate surface and the ends reach out of the first well region, however there is no intersection part, namely a corner part T part or cross part in the isolation trench. Therefore, no cavity occurs in the filler in the trench and stress is not concentrated on the intersection part. In addition, defects due to junction leak or mechanical damage do not occur, that is, there is no characteristic deterioration occuring. By providing the second well with memory cell, a semiconductor memory device whose characteristic defect rate and reliability defect rate are remarkably low can be formed.

Abstract: A semiconductor device comprising the fact that a semiconductor pellet is arranged on a substantially central part of a film base in which a metal plate is overlaid with an insulating member, while inner leads are arranged on a peripheral part of the film base in a state in which they are electrically isolated from the metal plate of the film base, and that external terminals for a power source among external terminals of the semiconductor pellet and middle parts of the metal plate of the film base, and inner leads for the power source among the inner leads and peripheral parts of the metal plate are electrically connected by pieces of bonding wire, respectively.