Abstract: A static random access memory device is provided with an internal activation signal generator and circuit means for overriding application of the internal activation signals to the memory circuit under predetermined circumstances. In normal read/write operation modes, word lines and a sense amplifier are activated only during a predetermined period in response to the internal activation signals in order to reduce power consumption. On the other hand, in a test mode, since the circuit means detects a higher voltage level of a predetermined external terminal of the device, the internal activation signals from the pulse generator are not used to limit the operating time of the word lines and sense amplifier. Therefore, during the test mode, the word lines and the sense amplifier are activated for a longer period than during the normal read/write operation mode. Because of this, the device is able to shorten aging time which occurs in the test mode.

Abstract: A writing high voltage of one polarity or an erasing high voltage of another polarity is selectively fed, in accordance with a writing or erasing operation mode, via a switch MOSFET to the word line of a non-volatile memory element designated by an address signal. The potential of a well region, where the switch MOSFET is existent, is changed in conformity with the switching action of the relevant switch MOSFET so as to control the switch MOSFET. Due to this arrangement, the potential of the well region with the non-volatile memory elements existing thereon can be retained at a fixed value, so that the high voltage generator is required merely to drive the selected word line of the memory array (and not the well in which the memory elements are formed). Consequently, the requisite current supply capability of the high voltage generator can be diminished.

Abstract: Disclosed are measurement (observation) pads for judging whether or not a dynamic random access memory (DRAM) adopting a shared sense system is functioning as designed. Concretely, measurement pads are formed by the step of forming a second layer of wiring respectively connected to pairs of complementary data lines which are formed by the step of forming a first layer of wiring, and the signal waveforms of the pairs of complementary data lines are measured using the measurement pads. Further, the measurement pads are provided between wiring layers which become fixed potentials in, at least, the operation of measuring data. In addition, each of the measurement pads is used in common by data lines which are respectively connected to two memory cells located in different memory cell mats.

Abstract: A semiconductor chip package technology which uses thin film wiring from the chip to the package terminals for increased line density and decreased parasitic capacitance and uses a thin film adhesion layer for improved heat conductivity between the package substrate and its sealing cap. The package uses a thin conductor film deposited along the element mounting surface of a sintered substrate. An adhesion layer, to provide a high quality bond between the sealing cap and substrate, is then deposited on the substrate peripheral area by successively laminating metal and metallized layers, or by depositing a single layer of low metal glass. The adhesion layer is thinner and of larger area than thick film technology, for improved heat conduction.

Abstract: A semiconductor memory wherein an operating mode is selectively set by effecting bonding with respect to predetermined pads provided on a common semiconductor substrate in a predetermined combination or by cutting off predetermined fuse means provided on the common semiconductor substrate in a predetermined combination and a bit pattern is selectively set by changing a part of a photomask applied to the common semiconductor substrate.

Abstract: A semiconductor integrated circuit device enabled to perform both a normal writing operation using a voltage elevated with the internal supply voltage taken as the reference voltage and a writing operation with the use of another voltage elevated with an external voltage applied to an external terminal taken as the reference voltage, whereby margin measurement, high-voltage test, and accelerated test are enabled to be performed even after packaging. Further, by providing the apparatus with a mode selector having a plurality of latch circuits operating at different timing connected to an input terminal so that modes are switched by changing combination of the signals latched in such latch circuits, the number of operating modes can be increased without increasing the number of pins.

Abstract: An ECL circuit wherein a current switch and an emitter follower are coupled, is so constructed that, in a standby mode, the current switch has its current cut off or rendered smaller than in an operating mode. In addition, the ECL circuit comprises means for decoupling a load resistance of the current switch and a base of the emitter follower in the case of cutting off the current of the current switch, or means for increasing the load resistance of the current switch in the case of rendering the current of the current switch smaller. The semiconductor circuit of the present invention can reduce the power consumption of the ECL circuit and can suppress fluctuations in the voltage levels of the outputs of the ECL circuit.

Abstract: Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.

Abstract: A memory area within a semiconductor integrated circuit device is accessible through an address changeover circuit. External control signals instruct the memory device as to the addressing mode desired. Address signals originating externally are provided directly to the IC's address decoder circuits, while addresses originating internal to the IC are first shifted one or two bits to modify the address by a power of 2, then provided to the address decoder circuits. In this way, data of bit length N may be written to a memory array of bit length M, where M>N.

Abstract: A semiconductor memory device has a sense amplifier which is constructed with a level shift circuit having an input which senses the change in a data line from an initial precharged level to a level near the vicinity of the supply voltage level which corresponds to data reading amounts from a memory cell during the reading mode of operation of the memory. The level shift circuit, in response to a memory cell reading signals, provides a level shifted output to the input terminal of a differential sense amplifier circuit, the level shifted output being in the vicinity of the operating point of the differential sense amplifier circuit. The level shift circuit includes a current amplifier having an output terminal that is formed with a series connecting node of a current amplifying transistor and a current source.

Abstract: Each memory cell of the memory array has a latch circuit, such as a pair of cross-connected CMOS inverters, for storing information, a first switch MOSFET whose gate is connected with a word line, and a second switch MOSFET which is connected in series with the first switch MOSFET and the gate of which is connected with the output terminal of the latch circuit. The first and second switch MOSFETs are coupled between the data line and a terminal supplied with a first power source voltage level, such as reference ground potential. Such memory cells are disposed at intersections of a plurality of data lines and a plurality of word lines. One of the plurality of data lines is connected with a common data line through a column switch which is alternatively brought into an ON state.

Abstract: An A/D converter included in an echo canceller or the like is furnished with a plurality of rate changing filters that receive the output signals of an oversampling A/D conversion circuit in common, the integration phases of the filters are different from each other as they are selectively advanced or retarded for each one of a plurality of predetermined intervals, and further furnished with an output selection circuit by which internal digital signals delivered as outputs from one of the rate changing filters are selectively transmitted according to the desired phase change.

Abstract: A semiconductor logic device having arrays of logic elements and chains of logic cells alternately arranged in a direction substantially perpendicular to the direction of the chains of logic cells in a surface portion of a semiconductor substrate. Each of the logic element arrays has input and output leads extending from the array in the above-mentioned direction substantially perpendicular to the direction of the chains of logic cells so that each of said logic cell chains is in an electrical connection with two adjacent logic element arrays via the input and output leads.

Abstract: The present invention discloses a suitable mounting of a wafer scale LSI (wafer scale integration) (WSI) in which a slit formed in a wafer is fit to a connector, a U-shaped reinforcing rubber member is disposed at the circumferential edge of the wafer, or a flexible adhesive is used for bonding a substrate formed with through-holes and a wafer, to provide a WSI mounting structure of high integration degree and high reliability. Furthermore, a method of efficient mounting by conducting the wiring of the wafer and the connection with the external terminal of the chip in one identical production step is disclosed.

Abstract: A processing apparatus includes a processing chamber and an insertion jig for inserting an object to be processed into the processing chamber. The processing chamber and the insertion jig are adapted to be individually movable relative to a heating section, so that the operation of loading and unloading the object into and from the processing chamber effected by the insertion jig is conducted outside the heating section, thereby preventing the outside air from being induced to enter the heated processing chamber, together with the object of the processing, and thus avoiding the occurrence of various problems, for example, the object of processing being disorderly oxidized by the oxygen contained in the outside air, and the foreign matter contained in the outside air being undesirably attached to the surface of the object, so as to obtain excellent processing results.

Abstract: In a single chip processor which can be provided with an extended program memory, a high-speed access can be executed without being restricted by the access time for the external program memory when an internal program memory is employed, by varying the effective instruction cycle, and thus a high-speed processing performance for a single chip processor of a stored program type can be attained.

Abstract: A semiconductor memory wherein an operating mode is selectively set by effecting bonding with respect to predetermined pads provided on a common semiconductor substrate in a predetermined combination or by cutting off predetermined fuse means provided on the common semiconductor substrate in a predetermined combination and a bit pattern is selectively set by changing a part of a photomask applied to the common semiconductor substrate.

Abstract: A semiconductor memory device is provided which includes a plurality of word line drivers and logic decoding circuitry coupled to the inputs of the word line drivers. In large memory arrays, the word line driver circuits can place large capacitive loads on the output of the logic decoding circuit because the word line driver transistors must be relatively large. This large load on the logic decoding circuitry adversely effects the operating speed of the memory. Accordingly, to reduce this load, a switching arrangement is provided between the output of the logic decoding circuitry and the word line drivers. This switching arrangement can be controlled to respectively connect the output of the logic decoding circuit to the word line drivers based on control output signals of a pre-decoder. Reset MOSFETs can also be provided to prevent the inputs of the word line drivers from floating.

Abstract: A semiconductor memory is provided with a first memory cell group, a second memory cell group, a first register for a serial output operation for holding information related to the first memory cell group, a second register for a serial output operation for holding information related to the second memory cell group, and transfer means for transferring information related to either the first or second memory cell group to either the first or second serial output register. By virtue of this arrangement, while the information transferred to the first serial output register is being serially output therefrom, information can simultaneously be transferred to the second serial output register by the transfer means.

Abstract: According to the present invention, as improvement in the adhesion of inner leads with a packaging resin in a resin-sealed semiconductor device is attained by spreading leads on or near the circuit-forming face of a pellet, or on or near the main non-circuit-forming face of the pellet to extend the lengths of the inner leads on or under the pellet.