Abstract: Each of a plurality of memory arrays is divided into a plurality of memory mats MAT00L-MAT07L to MAT10R-MAT17R in directions in which word lines and bit lines extend. First common data lines, that is, sub-IO lines, are provided which correspond to these memory mats and which are disposed in parallel to the word lines. Bit lines designating the corresponding memory mats are selectively connected to the first common data lines. Second common data lines, that is, main IO line groups MIOG0-MIOG7, are also provided and are disposed in parallel to the bit lines. Designated sub-IO lines are selectively connected to the second common data lines. Moreover, a plurality of main amplifiers forming a main amplifier unit MAU0 are orderly arranged in the direction in which the bit lines extend.

Abstract: Disclosed is a one-chip ULSI which can carry out fixed operations for a wide range of power supply voltages (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which provides a fixed internal voltage for a wide range of power supply voltages, an input/output buffer which can be adapted to several input/out interface levels, a dynamic or volatile RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

Abstract: There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.

Abstract: A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed.

Abstract: According to one aspect of the present invention, a semiconductor chip, which can be mounted in a zigzag in-line type package (ZIP) partially using a tabless lead frame, includes bonding pads arranged on the chip so that the chip can be applied also to other different types of packages. These different types of packages include a small out-line J-bent type package (SOJ) which uses a lead frame with tab, and a dual in-line type package (DIP) which uses a tabless lead frame. Further, a plurality of bonding pad pairs are provided amongst the bonding pads on the chip, each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to make the semiconductor chip compatible with a variety of or different types of packages.

Abstract: A non-shared system with respect to an outside and an inside cache in a multi-processor system has multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to the transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated in either copy back or write once system.

Abstract: A semiconductor integrated circuit is disclosed, in which a group of sense amplifiers activated at the same time by a selection signal on a selection signal line are divided into a plurality of blocks, and a power-source line for driving sense amplifiers is formed for each sense amplifier block so as to cross the selection signal line. Alternatively, an input/output line is divided into a plurality of sub-input/output lines, and a plurality of input/output lines are formed so that each input/output line crosses its sub-input/output lines, to form a hierarchical structure with respect to input/output lines. Thus, the load capacitance of each power-source line is reduced, and the time constant of each of the charging and discharging of the load capacitance is decreased. That is, the above semiconductor integrated circuit can operate at high speed.

Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

Abstract: There is disclosed a pipelined A/D converter including a plurality of A/D-D/A sub-blocks and one A/D sub-block successively connected in cascade form to determine a conversion output by several partial bits beginning from the most significant bit. Each of A/D-D/A sub-blocks includes a sample-and-hold circuit for successively sampling and holding an input analog signal fed to the sub-block, a partial A/D converter for performing A/D conversion on a hold output of this sample-and-hold circuit, a latch circuit for latching outputs of the partial A/D converter, a D/A converter for inversely converting outputs of the latch circuit to an analog signal, and a chopper amplifier for sampling the hold output of the sample-and-hold circuit with a delay of half a period, amplifying a difference between the sampled value and the inverse conversion output of the D/A converter during a succeeding interval of amplify mode, and outputting the amplified difference to a sub-block of a succeeding stage as a conversion residue.

Abstract: A silicone resin is applied on a substrate to form a coating film. The coating film is subjected to a reactive ion etching in an atmosphere containing at least O.sub.2. Thus, the film is inorganized in its surface and has a distribution of the residue, an organic radical, contained therein gradually increasing in the depth thereof. This permits an insulating film having excellent heat endurance to be formed without generation of any cracks. This insulating film is very useful as an interlayer insulating film for multi-layer wiring.

Abstract: A method of fabrication comprising forming a semiconductor integrated circuit device LSI which has a microcomputer CPU furnished with an EPROM, determining a program for controlling the microcomputer CPU and to be set in the EPROM (performing an initial evaluation) while information is being written into and erased from the EPROM built in the semiconductor integrated circuit device LSI, and thereafter forming a semiconductor integrated circuit device LSI in which the EPROM of the first-mentioned semiconductor integrated circuit device LSI is replaced with a mask ROM. In replacing the EPROM with the mask ROM, peripheral circuits required for both the EPROM and the mask ROM have their circuit arrangements held basically the same, and specific peripheral circuits for use in only the EPROM have their circuit regions left as they are as logically inactive regions.

Abstract: An output circuit is provided which includes a first switch coupled between a first power supply terminal and an output terminal, a second switch coupled between the first power supply terminal and the output terminal, an arrangement to set the output terminal at a high impedance state, and a first variable delay coupled to a first input terminal for turning on the first switch and the second switch with different timing from each other and for turning off the first switch and the second switch simultaneously. In addition, the output circuit includes a third switch coupled between the output terminal and a second power supply terminal, a fourth switch coupled between the output terminal and the second power supply terminal, and a second variable delay coupled to a second input terminal for turning on the third switch and the fourth switch with different timing from each other and for turning off the third switch and the fourth switch simultaneously.

Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

Abstract: The present invention is intended to operate a semiconductor device at high speed with low voltage. A circuit configuration is used in which the transfer impedance between a common I/O line and a data line is changed depending on whether information is to be read or written. A current/voltage converter is provided which includes a MISFET different in conduction type to a select MISFET. Thus, the speed of reading information is increased. An intermediate voltage generator having high driving capability is provided. Thus, the circuit has sufficient driving capability for an LSI having large load capacitance. A voltage converter is provided which converts a data line supply voltage or word line supply voltage to a higher voltage. Therefore, stabilized signal transmission is ensured.

Abstract: A signal transmission circuit in which a signal is converted into two complementary signals which are outputted from a signal transmission circuit via series resistors. The amplitude of each of the complimentary signals is reduced by the series resistors and terminating resistors provided on a signal receiving side. The signal receiving side shifts the level of the signals which it inputs. The level shifted signals are amplified by a high-input impedance differential amplifying circuit.

Abstract: Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

Abstract: In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.

Abstract: Means for changing-over address signals is provided in an address input portion, and the order of the signals to be input to an address decoder is changed according to external control signals. Alternatively, a reading output circuit is provided which reads data in bit unit different from that of the writing input circuit. Thus, data can be read and written even when the number of bits of data differs between in case of accessing a built-in memory of an LSI inside the LSI and in case of accessing it from outside the LSI.

Abstract: Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.

Abstract: A multi-layer leadframe according to this invention is formed by laminating on a leadframe body an insulating layer and an electrically conductive layer in this order. The electrically conductive plate includes a planar portion and a given number of terminal portions extending therefrom, said planar portion extending across said insulating layer laminated on said leadframe body. The planar portion is made thinner than the terminal portions. A thin portion of this planar portion is formed by an etching technique, and at least a part of the terminal portions of the electrically conductive plate is fixedly connected with an inner lead of the leadframe body.