Abstract: A semiconductor device includes: a unit configured to, in a period before power up, compare a voltage obtained by dividing a voltage of a first voltage node at a first division ratio with a voltage obtained by dividing a voltage of a second voltage node at a second division ratio and determine whether to activate an enable signal according to a result of the comparison; and a voltage driving unit configured to increase the voltage of the second voltage node when the enable signal is activated in the period before power up.

Abstract: A method for fabricating a semiconductor device includes forming first plugs over a substrate, forming contact holes that expose the first plugs, ion-implanting an anti-diffusion material into the first plugs, and forming second plugs filling the contact holes.

Abstract: A semiconductor memory device according to an aspect of the present disclosure includes a first page buffer coupled to a first even bit line and a first odd bit line, a second page buffer coupled to a second even bit line and a second odd bit line, and a controller configured to control the first and the second page buffers so that the second page buffer sets the second even bit line in a floating state such that the voltage of the second even bit line is changed according to a shift in the voltage of the first odd bit line, when a read operation for memory cells coupled to the first odd bit line is performed, and the second page buffer stores data corresponding to the level of threshold voltages of the memory cells by detecting a shift in the voltage of the second even bit line.

Abstract: In a method for fabricating a magnetic tunnel junction, a first magnetic layer is formed on a substrate, and a tunnel insulating layer is formed on the first magnetic layer. Subsequently, a second magnetic layer is formed on the tunnel insulating layer. In the method, the first magnetic layer is formed by periodically sputtering a magnetic target while a metal target is continuously sputtered.

Abstract: The present invention relates to a substrate for a semiconductor package and a semiconductor package having the same. A substrate for a semiconductor package includes a substrate body; a contact pad group including a plurality of contact pads parallely arranged at a determined interval on a surface of the substrate body; dummy contact pads arranged at both sides of the contact pad group, respectively; and solder resist patterns covering the substrate body and having openings exposing the dummy contact pads and the contact pad group. When bumping the semiconductor chip having the bumps to the solders arranged on the contact pads formed on the substrate, the bumping defect caused due to different volumes of each solder can be prevented.

Abstract: A semiconductor device capable of ensuring a sufficient area of a peripheral region by forming a gate spacer to have a uniform thickness in the peripheral region and reducing a fabrication cost by simplifying a mask process and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a gate disposed over a semiconductor substrate; a first spacer disposed over sidewalls of the gate; an insulating layer pattern disposed over sidewalls of the first spacer; and a second spacer disposed over the first spacer and the insulating pattern.

Abstract: A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.

Abstract: A nonvolatile memory device comprises a memory cell configured to store or output data in a magneto-resistance device in response to a write current applied to a bit line and a source line. A voltage detector is configured to sense potentials loaded in the bit line and the source line. A write current controller configured to control activation of a write control signal in response to an output of the voltage detector, and a write driver configured to control amounts of write current applied to the memory cell according to the activation of the write control signal.

Abstract: A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed information to generate an internal voltage having a different level depending on the operation speed; and an internal circuit operated using the internal voltage.

Abstract: A semiconductor device includes a code generator configured to generate a supplementary code with a value changing in response to a variation of an impedance code, a main driver configured to receive an output data and drive the received output data to a data output pad, wherein a driving force of the main driver is controlled according to the impedance code, and an auxiliary driver configured to receive the output data and drive the received output data to the data output pad, wherein a driving force of the auxiliary driver is controlled according to the supplementary code.

Abstract: A semiconductor device including a buried gate is disclosed. In the semiconductor device, a bit line contact contacts a top surface and lateral surfaces of an active region, such that a contact area between a bit line contact and the active region is increased and a high-resistivity failure is prevented from occurring in a bit line contact.

Abstract: A highly integrated phase change memory device and a method for manufacturing the same is disclosed. The highly integrated phase change memory device includes a semiconductor substrate having a cell area and a peripheral area with impurity regions formed in the cell area and extending in parallel to each other in a first direction to form a striped pattern. A gate electrode is formed in the peripheral area and dummy gate electrodes are formed in the cell area and extending in a second direction perpendicular to the first direction of the impurity regions. An interlayer dielectric layer pattern exposes portions of the cell area and the peripheral area and a PN diode is formed in a space defined by a pair of dummy gate electrodes and a pair of interlayer dielectric layer patterns.

Abstract: A method for operating a non-volatile memory device includes counting the number of consecutive verify operations performed without a precharge, sensing a temperature, and when the number of verify operations exceeds a set value of verify operations, controlling a level of a sensing bias voltage based on the sensed temperature.

Abstract: A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first bit line contact over a semiconductor substrate, forming a second bit line contact that is coupled to the first bit line contact and has a larger width than the first bit line contact, and forming a bit line over the second bit line contact. When using the semiconductor device having a buried gate, although the bit line is formed to have a small width and the bit line pattern is misaligned, the method prevents incorrect coupling between a bit line and a bit line contact, so that it basically deteriorates unique characteristics of the semiconductor device.

Abstract: A nonvolatile memory device includes a memory cell array configured to comprise a number of cell strings, a number of page buffers each coupled to the cell strings of the memory cell array through bit lines, and a bit line precharge circuit configured to precharge a selected bit line up to a voltage of a first level before one of the page buffers precharges the selected bit line.

Abstract: A method for fabricating a nonvolatile memory device includes forming a substrate structure having a tunnel dielectric layer and a floating-gate conductive layer formed over an active region defined by a first isolation layer forming a first inter-gate dielectric layer and a first control-gate conductive layer over the substrate structure, forming a trench by etching the first control-gate conductive layer, the first inter-gate dielectric layer, the floating-gate conductive layer, the tunnel dielectric layer, and the active region to a given depth, forming a second isolation layer to fill the trench; and forming a second control-gate conductive layer over the resultant structure having the second isolation layer formed therein.

Abstract: A nonvolatile memory device includes a first channel comprising a pair of first pillars vertically extending from a substrate and a first coupling portion positioned under the pair of first pillars and coupling the pair of first pillars, a second channel adjacent to the first channel comprising a pair of second pillars vertically extending from the substrate and a second coupling portion positioned under the pair of second pillars and coupling the pair of second pillars, a plurality of gate electrode layers and interlayer dielectric layers alternately stacked along the first and second pillar portions, and first and second trenches isolating the plurality of gate electrode layers between the pair of first pillar portions and between the pair of second pillar portions, respectively.

Abstract: A method for forming a highly integrated semiconductor device having multiplayer conductive lines is presented. The method includes the operations of forming, etching, burying and forming. The first forming operation includes forming a line-type conductive layer on a semiconductor substrate including a buried gate to expose the gate. The etching operation includes etching the conductive layer to expose at least a region between one side of an active area defined in the semiconductor substrate and an opposite side of the neighboring active area, both the active areas being arranged next to each other in a major axis direction of the gate. The burying operation includes burying a first insulating film in the etched line-type conductive layer. The second forming operation includes forming a bit line passing through the center of the active area in a direction perpendicular to the major axis direction of the gate.

Abstract: A method for fabricating a semiconductor device includes: forming a first photoresist pattern with a first opening over an etch target layer; forming a second photoresist pattern with a plurality of second openings over the first photoresist pattern; and forming a plurality of patterns by etching the etch target layer by using the first photoresist pattern and the second photoresist pattern as an etch barrier.

Abstract: A nonvolatile memory device includes a control unit configured to measure a threshold voltage distribution of each of selected pages between a start voltage and an end voltage by performing a read operation on each page in response to a command set for analyzing the threshold voltage distribution, to compare the measured threshold voltage distribution with a reference threshold voltage distribution, and to determine a read voltage having a least amount of errors upon the read operation being performed.