Abstract: A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.

Abstract: An apparatus and method is capable of reducing instantaneously consumed current by allowing write drivers and input buffers not to be simultaneously driven in a multi-test of semiconductor chips. A multi-test apparatus includes an input unit configured to receive data for testing, wherein the data for testing is inputted from a circuit outside of the multi-test apparatus, a plurality of memory banks each including a plurality of memory cells, a plurality of write drivers, corresponding to the respective memory banks, configured to write the test data in the plurality of memory banks, and a write control unit configured to control the plurality of write drivers so that the test data is written in the memory banks in at least two time periods.

Abstract: An image sensor includes: a substrate having a plurality of unit pixel region; a light receiving element formed in the substrate at the unit pixel region; an interlayer dielectric layer formed over the substrate; a lightguide formed in the interlayer dielectric layer for the light receiving element; a light focusing pattern formed over the interlayer dielectric layer at the pixel region; a planarization layer formed over the substrate and covering the light focusing pattern; and a lens formed over the planarization layer at the pixel region.

Abstract: A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock.

Abstract: A method for manufacturing a semiconductor device is disclosed. In the method for manufacturing the semiconductor device, a capacitor structure is modified to ensure capacitance of the capacitor, and the height of the capacitor is reduced to prevent defects such as a leaning capacitor or a poor bridge from being generated, such that the fabrication process of semiconductor devices is simplified and therefore the semiconductor devices can be stably manufactured.

Abstract: An operating method of a semiconductor device that includes a plurality of memory cell blocks, comprising selecting one of the memory cell blocks in response to a program command, performing a pre-program operation and a pre-erase operation so that threshold voltages of memory cells included in the selected memory cell block are distributed between a first positive voltage and a first negative voltage, supplying a program permission voltage to a first group of bit lines and supplying a program inhibition voltage to a second group of bit lines, wherein the first group and the second group are mutually exclusive, and supplying a positive program voltage to a selected word line coupled to memory cells.

Abstract: A test method for a memory having first and second cell arrays, first compressed data obtained by compressing output data of the first cell array and output data of the second cell array is outputted. When the first compressed data represents that a fail exists, output data of one of the first and second cell arrays is locked as normal data, and second compressed data obtained by compressing the normal data and output data of the other of the first and second cell arrays is outputted.

Abstract: An integrated circuit includes a first semiconductor chip including a plurality of first through chip vias for a first voltage and a plurality of second through chip vias for a second voltage inserted in vertical direction. A second semiconductor chip is stacked over the first semiconductor chip, and includes the plurality of first through chip vias and the plurality of second through chip vias. The plurality of first connection pads is configured to couple the first semiconductor chip to the second semiconductor chip, by coupling the corresponding first through chip vias. The plurality of second connection pads is configured to couple the first semiconductor chip to the second semiconductor chip, by coupling the corresponding second through chip vias. A first conductive line is configured to couple the plurality of first connection pads to each other, and a second conductive line is configured to couple the plurality of second connection pads to each other.

Abstract: A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having first active region and a second active region. The latter has a second recess region formed in lower portion of the active region than the former. A step gate pattern is formed on border region between the first active region and the second active region. The gate pattern has step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.

Abstract: A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit which delays a sense amplifier enable signal in response to the first and second detection signals and generates first through third control signals. The enable period of the first and second control signals are controlled based on the levels of the first and second detection signals.

Abstract: A semiconductor memory device includes a pipe latch circuit configured to receive parallel input data and output serial data or set an output terminal of the pipe latch circuit at a predetermined voltage level in response to an enable signal, and a synchronization circuit configured to output an output data of the pipe latch circuit in synchronization with an internal clock.

Abstract: The data input circuit of a nonvolatile memory device includes a redundancy multiplexer configured to selectively output normal data and redundancy data to an internal global data line in response to a redundancy signal, a plurality of pipe registers coupled to the internal global data line and configured to latch normal data or redundancy data received through the internal global data line in response to a plurality of respective latch signals, and an output multiplexer configured to sequentially output the latched data in response to a plurality of selection signals.

Abstract: An electrostatic discharge protection circuit includes a diode chain coupled between a power supply voltage end and a control node, a control voltage generator configured to generate a control voltage in response to a first current flowing through the diode chain, and a discharger configured to discharge a second current from the power supply voltage end to a ground voltage end in response to the control voltage, wherein the diode chain includes a plurality of P-well regions formed in an N-well region, diodes formed in the respective P-well regions, and a resistor coupled between the diodes.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.

Abstract: A program method of a nonvolatile memory device includes programming data of a first bit into a target page of a plurality of pages in a memory cell array, sensing the programmed data and storing the sensed data in a page buffer coupled to the memory cell array, erasing data of the target page, inputting data of a second bit to the page buffer and generating program data by combining the data of the second bit and the data of the first bit stored in the page buffer, and programming the program data into the target page.

Abstract: A semiconductor device comprises a buried gate formed by being buried under a surface of a semiconductor substrate, a dummy gate formed on the buried gate, and a landing plug formed on a junction region of the semiconductor substrate being adjacent to the dummy gate.

Abstract: A semiconductor memory device includes: an internal clock signal generation unit configured to generate an internal clock signal in response to an external clock signal; an internal data strobe signal generation unit configured to generate an internal data strobe signal in response to an external data strobe signal; a phase comparison unit configured to compare phases of the internal clock signal and the internal data strobe signal that are used in an enabled write path in response to an internal dummy write command with each other; and an output unit configured to output an output signal of the phase comparison unit.

Abstract: An impedance calibration circuit for impedance matching between a semiconductor memory device and an external device includes a driving circuit and a comparing circuit. The driving circuit has a plurality of internal resistances, with one or more of the internal resistances being a variable resistance. The driving circuit compares the impedance of the internal resistances to the input/output impedance of the external device in order to provide a calibration voltage. The comparing circuit compares the calibration voltage to a reference voltage and provides a code signal for calibrating the impedance corresponding to output data with the input/output impedance of the external device. The impedance calibration circuit calibrates an impedance mismatch between the impedance calibration circuit and a data input/output driver by adjusting the impedance of the impedance calibration circuit through the variable resistance.

Abstract: A semiconductor memory device includes a random address generation unit configured to receive a multi-bit source address and generate a multi-bit random address and a signal mixing unit configured to mix the multi-bit random address with a data, wherein the random address generation unit has a plurality of transmission lines configured to electrically connect the plurality of input terminals respectively corresponding to bits of the source address and the plurality of output terminals respectively corresponding to bits of the random address in one-to-one correspondence regardless of an order of the bits of the source address.

Abstract: A semiconductor device includes an internal voltage input buffer configured to determine voltage levels of a pull-up driving node and a pull-down driving node as a result of a comparison between a voltage level of an internal voltage node and a voltage level of a reference voltage node such that the pull-up driving node and the pull-down driving node to maintain a voltage level difference, and an internal voltage driving block configured to pull-up drive the internal voltage node in response to the voltage level of the pull-up driving node and pull-down drive the internal voltage node in response to the voltage level of the pull-down driving node.