Patents Assigned to Hynix Semiconductor
  • Sense-amp transistor of semiconductor device and method for manufacturing the same
    Patent number: 8748978
    Abstract: A sense-amp transistor for a semiconductor device and a method for manufacturing the same are disclosed. A sense-amp transistor for a semiconductor device includes a recess array formed in a gate region of a sense-amp, a plurality of buried gates formed in each recess of the recess array so as to form a vertical channel region, and an upper gate configured to form a horizontal channel region in an active region between the buried gates. As a result, the number of additional processes is minimized, and the sensing margin of the sense-amp is guaranteed.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: June 10, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Ho Lee
  • Pipe latch circuit and driving method thereof
    Patent number: 8742812
    Abstract: A pipe latch circuit includes a pipe input unit configured to receive a plurality of data in an order corresponding to address information, a control signal generator configured to generate first and second control clock signals by using the address information, where the first and second control clock signals correspond to a synchronization clock signal, and a pipe output unit configured to synchronize an output signal of the pipe input unit with the first and second control clock signals and output the synchronized output signal.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: June 3, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae-Il Kim
  • Data transfer circuit and memory device having the same
    Patent number: 8745288
    Abstract: A data transfer circuit includes a serial-to-parallel converter configured to convert multi-bit data inputted in series into parallel data by controlling the number of bits of the parallel data and a conversion timing based on an operation mode, and a data transmission unit configured to transfer the parallel data to a first data path or a second data path based on the operation mode.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: June 3, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyoung-Jun Na, Jae-Il Kim
  • Semiconductor device with one-side contact and fabrication method thereof
    Patent number: 8742548
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of first trenches by etching a substrate, forming first spacers covering both sidewalls of each of the first trenches, forming a plurality of second trenches by etching a bottom of each of the first trenches, forming second spacers covering both sidewalls of each of the second trenches, forming a plurality of third trenches by etching a bottom of each of the second trenches, forming an insulation layer covering exposed surfaces of the plurality of the substrate, and forming a contact which exposes one sidewall of each of the second trenches by selectively removing the second spacers.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: June 3, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: You-Song Kim
  • Semiconductor device with a gate having a bulbous area and a flattened area underneath the bulbous area and method for manufacturing the same
    Patent number: 8741716
    Abstract: A semiconductor device with a gate having a bulbous area and a flattened area underneath the bulbous area is presented. The semiconductor device includes a semiconductor substrate, an isolation layer, a gate insulation layer, and gates. The semiconductor substrate has recess parts that have first grooves which have bulbous-shaped profiles and second vertically flattened profile grooves which extend downward from the first grooves. The gates are formed in the recess parts in which the gate insulation layer is double layered in the bulbous profile areas and is single layered in the flattened profile areas.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: June 3, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Gil Chun
  • Semiconductor device and method of fabricating the same
    Patent number: 8741734
    Abstract: A semiconductor device includes a semiconductor substrate having a trench defining an active region. A wall oxide is formed on side walls of the active region extending in the longitudinal direction, and an element isolation layer is formed in the trenches. A method of manufacturing a semiconductor device includes forming line-shape first trenches on a semiconductor substrate so as to define an active region; forming a wall oxide on surfaces of the first trenches; forming a second trench which separates the active region into a plurality of active regions; and filling the trenches with an element isolation layer.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: June 3, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Bum Kim
  • Semiconductor device and semiconductor system including the same
    Patent number: 8738955
    Abstract: A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: May 27, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jung-Hoon Park
  • Semiconductor memory device for transferring data at high speed
    Patent number: 8737145
    Abstract: A semiconductor memory device includes: a data multiplexing unit configured to output one of a data training pattern and data transferred through a first global input/output line in response to a training control signal; and a latch unit configured to latch an output of the data multiplexing unit to apply and maintain the latched output to a second global input/output line.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: May 27, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ji-Hyae Bae, Sang-Sik Yoon
  • Semiconductor memory device and method of testing the same
    Patent number: 8737152
    Abstract: A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second sense amplifier coupled to a second bit line of the first mat and a third bit line of the second mat, a third sense amplifier coupled to a fourth bit line of the second mat, and a plurality of bit line precharge voltage providers for varying a level of a bit line precharge voltage provided to the first, second, and third sense amplifiers, selectively providing the resultant bit line precharge voltage level, and providing the same voltage as that of data of a selected cell to a non-selected sense amplifier during a read operation.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 27, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Suk Min Kim
  • Semiconductor device and method for manufacturing the same
    Patent number: 8735956
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. An additional spacer is formed at a lateral surface of an upper part of the bit line so that the distance of insulation films between a storage node and a neighboring storage node contact plug is increased. Accordingly, the distance between the storage node and the neighboring storage node contact is guaranteed and a bridge failure is prevented.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 27, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Un Hee Lee
  • Semiconductor memory device having redundancy circuit for repairing defective unit cell
    Patent number: 8737146
    Abstract: A semiconductor memory device includes a first bank including a plurality of cell matrices a second bank including a plurality of cell matrices and a shared-fuse set, which is shared by the first and second banks, configured to output a defect indication signal when the first bank or the second bank is enabled and a defective cell matrix is included in the enabled bank.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: May 27, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwi-Dong Kim, Ki-Chang Kwean
  • Method for forming the semiconductor cell
    Patent number: 8728909
    Abstract: A semiconductor cell includes first trenches defining fin type active regions within the semiconductor substrate and adjacent to each other, second trenches disposed at one side and the other side of the first trenches, adjacent to the first trench and including fin type active regions, a first oxide layer formed on each of surfaces of the first trenches, and a second oxide layer formed on each of surfaces of the second trenches and having a thicker thickness than the first oxide layer. Although the critical dimension of the fin is increased, the gate drivability can be improved.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: May 20, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung Do Kim
  • Delay locked loop circuit and semiconductor device having the same
    Patent number: 8729940
    Abstract: A semiconductor device includes a delay line configured to delay a source clock by a delay equal to a first number of delay units in response to a delay control code and to generate a delayed source clock; a delay amount sensing unit configured to sense whether the delay amount of the delay line reaches a delay amount limit; a clock cycle measuring unit configured to measure the cycle of the source clock by counting a sampling clock in response to an output signal of the delay amount sensing unit, wherein a cycle of the sampling clock is equal to a second number of delay units; and a delay amount controlling unit configured to change the delay amount of the delay line in response to the measured cycle of the source clock as determined from an output signal of the clock cycle measuring unit.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: May 20, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young-Jun Ku
  • Method for fabricating capacitor of semiconductor device
    Patent number: 8728887
    Abstract: A method for fabricating a capacitor of a semiconductor device includes sequentially forming an etch-stop layer and a mold layer over a substrate, sequentially forming a support layer and a hard mask pattern over the mold layer, forming a storage node hole by etching the support layer and the mold layer using the hard mask pattern as an etch barrier, forming a barrier layer on the sidewall of the mold layer inside the storage node hole, etching the etch-stop layer under the storage node hole, forming a storage node inside the storage node hole, and removing the hard mask pattern, the mold layer, and the barrier layer.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: May 20, 2014
    Assignee: Hynix Semiconductor
    Inventors: Jeong-Yeop Lee, Hyung-Soon Park, Young-Bang Lee, Su-Young Kim
  • Magnetic tunnel junction and spin transfer torque random access memory having the same
    Patent number: 8730714
    Abstract: A magneto-resistance memory device includes a first pinned layer having a first magnetic polarity regardless of current applied to the first pinned layer, a first tunnel insulating layer arranged on the first pinned layer, a first free layer arranged on the first tunnel insulating layer and having a magnetic polarity that changes in response to current of a first amount, a second pinned layer coupled to the first free layer and having the first magnetic polarity regardless of current applied to the first pinned layer, a second tunnel insulating layer arranged on the second pinned layer, a second free layer arranged on the second tunnel insulating layer and having a magnetic polarity that changes in response to current of a second amount, wherein the second amount is smaller than the first amount, and a connection layer.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: May 20, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Hyun Lee
  • Method of programming a semiconductor memory device
    Patent number: 8730735
    Abstract: A method of programming a semiconductor memory device by applying a program voltage to a selected word line in an incremental step pulse program mode includes raising a voltage of precharging a bit line for program inhibition according to an increase in the program voltage applied to the selected word line.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: May 20, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seong Je Park
  • Method for fabricating semiconductor device
    Patent number: 8728898
    Abstract: A method for fabricating a semiconductor device includes forming a mold layer over a substrate, wherein the mold layer includes a first sacrificial layer and a second sacrificial layer that are stacked, forming an insulation layer pattern that has an etch selectivity to the first sacrificial layer and the second sacrificial layer on the mold layer, etching the mold layer using the insulation layer pattern as an etch barrier to form storage node holes, forming a storage node conductive layer over a substrate structure including the insulation layer pattern and the mold layer that has been etched, performing a storage node isolation process that simultaneously forms storage nodes and forming the insulation layer pattern to a first thickness, and removing the first sacrificial layer and the second sacrificial layer.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: May 20, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Su-Young Kim
  • Memory cell of semiconductor memory device and method for driving the same
    Patent number: 8724418
    Abstract: A semiconductor memory device includes a first fuse having one end coupled with a first bit line and configured to be programmed with a data, a second fuse having one end coupled with a second bit line and configured to be programmed with the data; a program controller coupled with the other ends of the first fuse and the second fuse and configured to perform a program operation on at least one of the first fuse and the second fuse in response to a program voltage, and a read controller coupled with the other ends of the first fuse and the second fuse and configured to perform a read operation on the first fuse and the second fuse in response to a read voltage.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: May 13, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae-Hoon Kim, Sung-Mook Kim
  • Semiconductor device and method for driving the same
    Patent number: 8717072
    Abstract: A semiconductor device includes a comparison unit configured to compare the phases of a plurality of clocks having different frequencies and output a phase comparison signal, a phase inversion control unit configured to generate a phase inversion control signal, and a start control unit configured to generate a start control signal in response to a clock enable signal, wherein the comparison unit is configured to start an operation in response to the start control signal and invert, in response to the phase inversion control signal, a phase of an internal clock generated from one of the plurality of clocks when the plurality of clocks have different phases.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: May 6, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jung-Hoon Park
  • Flash memory device and mask for fabricating the same
    Patent number: 8716779
    Abstract: A flash memory device includes an active region, drain contacts, a source contact line, and source contacts. The active regions are formed on a substrate extend at least from a source region to a drain region of the substrate. The drain contacts are formed over the active regions in the drain region. The source contact line is formed in the source region of the semiconductor substrate. The source contact line intersects the active regions and is continuously line-shaped. The source contact line includes source contacts formed at locations where the source contact line and the active regions intersect. The source contacts are zigzag-shaped and are separated from corresponding drain contacts by a given distance.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: May 6, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Mi Hye Kim, Dong Sook Chang