Patents Assigned to Hynix Semiconductor
  • Method of operating nonvolatile memory device
    Patent number: 8767469
    Abstract: A method of operating a nonvolatile memory device includes performing a LSB program operation on memory cells coupled to a selected word line and a word line adjacent to the selected word line; performing a first MSB program operation so that the threshold voltages of the memory cells coupled to the selected word line reach temporary voltages lower than first target voltages; performing a second MSB program operation so that the threshold voltages of the memory cells coupled to the word line adjacent to the selected word line are higher than second target voltages; and performing a third MSB program operation so that the threshold voltages of the memory cells coupled to the selected word line are higher than the first target voltages.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: July 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ki Seog Kim
  • Clock transfer circuit and semiconductor device including the same
    Patent number: 8767503
    Abstract: A clock transfer circuit includes a clock transfer unit configured to receive an external clock and transfer the received external clock as one or more internal clocks and a clock control unit configured to control the clock transfer unit to transfer the external clock as a column clock among the internal clocks in response to an active command and block a transfer of the external clock as the column clock in response to a precharge command.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: July 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sun-Suk Yang
  • Semiconductor device and method of manufacturing the same
    Patent number: 8766333
    Abstract: A semiconductor device includes a first buried bit line (120a) provided between lower and upper substrates (100b, 100a), first and second pillar patterns (105a, 105b) extending from the upper substrate (100a) and coupled to the first buried bit line (120a) through first and second gate patterns (140a), respectively. A first body contact pattern (160a) coupled to the first and/or the second pillar patterns (105a, 105b) through the upper substrate (100a) prevents the first and the second pillar patterns from floating.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: July 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min Chul Sung
  • Semiconductor devices and method of manufacturing the same
    Patent number: 8766352
    Abstract: A semiconductor device includes a pipe channel layer formed over a substrate, a first vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a bit line, a second vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a source line, a multi-layer comprising a charge trap layer and formed to surround the first vertical channel layer, the second vertical channel layer, and the pipe channel layer, an insulating barrier layer formed to surround the multi-layer, a plurality of first conductive layers formed between the pipe channel layer and the bit line, wherein the first vertical channel layer passes through the first conductive layers, and a plurality of second conductive layers formed between the pipe channel layer and the source line, wherein the second vertical layer passes through the second conductive layers.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: July 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Kyun Jung
  • Semiconductor memory device and driving method thereof
    Patent number: 8767479
    Abstract: A semiconductor memory device using a termination scheme in a global data line includes a global data line and a data line drive unit. The global data line transfers data between an interface region and a plurality of core regions each having a memory bank. The data line drive unit is disposed in each of the core regions, and drives the data global line in response to data in a data transfer operation. The data line drive unit sets the global data line to a termination voltage level in a termination operation.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: July 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae-Woong Yun
  • Method of manufacturing non-volatile memory devices
    Patent number: 8765587
    Abstract: A method of manufacturing non-volatile memory devices includes forming a gate insulating layer and a first conductive layer over a semiconductor substrate, etching the first conductive layer and the gate insulating layer to expose part of the semiconductor substrate, forming trenches at a target depth of the semiconductor substrate by repeatedly performing a dry etch process for etching the exposed semiconductor substrate and a cleaning process for removing residues generated in the dry etch process, forming isolation layers within the trenches, forming a dielectric layer on a surface of the entire structure in which the isolation layers are formed, and forming a second conductive layer on the dielectric layer.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: July 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Su Hyun Lim, Seung Cheol Lee
  • Integrated circuit and semiconductor memory device using the same
    Patent number: 8769240
    Abstract: An integrated circuit includes a random address generation unit configured to generate a first random address for a data randomizing operation, an address conversion unit configured to convert the first random address and generate a second random address, and a synchronization output unit configured to sequentially output the first and second random addresses in synchronization with a clock signal.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: July 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dae-Il Choi
  • Non-volatile memory device with vertical memory cells
    Patent number: 8759902
    Abstract: A non-volatile memory device includes a plurality of gate electrodes stacked over a semiconductor substrate and stretched in a first direction along the semiconductor substrate and a plurality of junction layers having a first region protruding from the semiconductor substrate and crossing the gate electrodes and a second region formed between the gate electrodes.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 24, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jung-Ryul Ahn
  • Column circuit and pixel binning circuit for image sensor
    Patent number: 8759736
    Abstract: A column circuit for an image sensor includes a first column read circuit configured to read data of a first column line, and a second column read circuit configured to read data of a second column line, wherein, during a binning mode, data from two or more pixels are outputted through the first column line and stored in the first column read circuit in a first phase, data from two or more pixels are outputted through the second column line and stored in the second column read circuit in a second phase, and charges are shared between the first column read circuit and the second column read circuit in a third phase.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: June 24, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Si-Wook Yoo
  • 3-D structured non-volatile memory device and method of manufacturing the same
    Patent number: 8760934
    Abstract: A non-volatile memory device includes channel structures that each extend in a first direction, wherein the channel structures each include channel layers and interlayer dielectric layers that are alternately stacked; source structure extending in a second direction crossing the first direction and connected to ends of the channel structures, wherein the source structure includes source lines and interlayer dielectric layers that are alternately stacked; and word lines extending in the second direction and formed to surround the channel structures.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: June 24, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hack Seob Shin, Sang Hyun Oh
  • Semiconductor memory device integrating flash memory and resistive/magnetic memory
    Patent number: 8760920
    Abstract: A semiconductor memory device includes a first memory device formed on a semiconductor substrate, including a first storage unit, a source, and a drain, a second memory device, including a second storage unit, and a bit line, wherein the second memory device is connected in series between the bit line and the drain.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: June 24, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sook Joo Kim, Min Gyu Sung
  • Buffer circuit
    Patent number: 8760199
    Abstract: A buffer circuit includes an amplification unit configured to amplify and output a difference between an input signal and a reference voltage; and a driver configured to drive an output node in response to the output of the amplification unit and be controlled in at least one of a pull-up driving strength and a pull-down driving strength at the output node in response to the reference voltage.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: June 24, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Yeon Byeon
  • Semiconductor device having vertical channel transistor and method for fabricating the same
    Patent number: 8759906
    Abstract: A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: June 24, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Yong-Soo Kim, Kwan-Yong Lim
  • Semiconductor memory apparatus and data input/output method thereof
    Patent number: 8760960
    Abstract: A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to the second bit line; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines. A bank selection signal controls both the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: June 24, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung Wook Kwack, Kae Dal Kwack
  • Semiconductor system and device for identifying stacked chips and method thereof
    Patent number: 8760181
    Abstract: A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: June 24, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Jin Byeon, Jong-Chern Lee
  • Method for fabricating semiconductor device
    Patent number: 8759233
    Abstract: A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: June 24, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Hoon Cho
  • Semiconductor device having capacitors fixed to support patterns and method for manufacturing the same
    Patent number: 8753954
    Abstract: A semiconductor device containing a cylindrical shaped capacitor and a method for manufacturing the same is presented. The semiconductor device includes a plurality of storage nodes and a support pattern. The plurality of storage nodes is formed over a semiconductor substrate. The support pattern is fixed to adjacent storage nodes in which the support pattern has a flowable insulation layer buried within the support pattern. The buried flowable insulation layer direct contacts adjacent storage nodes.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: June 17, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Min Park
  • Three dimensional non-volatile memory device and method of manufacturing the same
    Patent number: 8748966
    Abstract: A three dimensional non-volatile memory structure includes a plurality of interlayer dielectric layers and a plurality of control gates alternately stacked over a substrate, a channel formed to penetrate the plurality of interlayer dielectric layers and the plurality of control gates, a tunnel insulating layer formed to surround the channel, a plurality of floating gates disposed between the plurality of interlayer dielectric layers and the tunnel insulating layer, wherein the plurality of floating gates each have a thickness greater than a corresponding one of the interlayer dielectric layers, and a charge blocking layer disposed between the plurality of control gates and the plurality of floating gates.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: June 10, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Jin Whang, Kwon Hong, Ki Hong Lee
  • Semiconductor device generating varied internal voltages
    Patent number: 8749299
    Abstract: The present invention describes a semiconductor device that generates internal voltages having different levels using an external voltage. The semiconductor device includes a plurality of asynchronous internal voltage generating circuits that share an external voltage source and generate internal voltages having different levels from one another. The plurality of asynchronous internal voltage generating circuits maintain the levels of the internal voltages at target levels by using the external voltage at different time points, respectively. The semiconductor device minimizes noise in the external voltage according to the use of the internal voltages.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: June 10, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Hoon Han, Woo Young Lee
  • Memory device and method for operating the same
    Patent number: 8750048
    Abstract: A memory includes at least one first flag cell configured to store first flag data, at least one second flag cell configured to store second flag data, at least one first sensing node having a voltage level determined by the first flag data of the first flag cell, at least one second sensing having a voltage level determined by the second flag data of the second flag cell, a selection circuit configured to select the first sensing node or the second sensing node in response to a flag address; and a determination circuit having an internal node through which current corresponding to a voltage level of a selected sensing node flows and configured to determine a logic value of flag data corresponding to the selected sensing node among the first and second flag data by using an amount of current flowing through the internal node.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: June 10, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Myung Cho, Seong-Je Park, Jung-Hwan Lee, Ji-Hwan Kim, Beom-Seok Hah