Abstract: A vertical semiconductor device includes a first active pillar vertically protruded from a semiconductor substrate; a first vertical gate connected to at least one side of the first active pillar and formed along a direction that crosses a buried bit line; and a first body line connected to at least one side of the first active pillar which is not connected to the first vertical gate.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.

Abstract: In a semiconductor device, a polysilicon layer of a lower electrode contact plug is removed by a strip process such that the deposition area of a dielectric film is increased and capacitance of a capacitor is assured. A method for manufacturing the semiconductor device is also disclosed.

Abstract: A system includes a first chip configured to supply a training command and a second chip configured to transfer to the first chip a measured time for performing an operation in response to the training command.

Abstract: A method of programming a nonvolatile memory device includes sequentially programming first to (n?1)th logical pages of all the physical pages of a first memory block of the memory blocks in response to a first program command, a step of loading data of the first to (n?1)th logical pages stored in a first physical page of the first memory block and latching the loaded data in first to (n?1)th latches of each of the page buffers, respectively, when receiving a second program command after programming all the first to (n?1)th logical pages, and latching new program data, received along with the second program command, in an nth latch of the corresponding page buffer and programming the data, stored in the first to nth latches of the page buffer, into a first physical page of a second memory block of the memory blocks.

Abstract: A program method of a semiconductor memory device includes performing a least significant bit (LSB) program operation for target LSB program cells of a selected page, increasing the threshold voltages of target most significant bit (MSB) program cells of the selected page before performing an MSB operation for the target MSB program cells, and performing the MSB program operation for the target MSB program cells after the increasing of the threshold voltages of the target MSB program cells.

Abstract: A power distributor includes a large reservoir capacitor, a switch coupled between at least one power supply line and the large reservoir capacitor, and a controller configured to turn on or off the switch based on whether a circuit block connected to the power supply line is in operation or not.

Abstract: A method of manufacturing a semiconductor device includes forming silicon line patterns in a semiconductor substrate, forming an insulating layer over the silicon line patterns, forming a conductive pattern between the silicon line patterns, forming a spacer over the substrate, forming an interlayer insulating layer between the silicon line patterns, removing the spacer on one side of the silicon line patterns to expose the conductive pattern, forming a bit line contact open region by removing the interlayer insulating layer, forming a polysilicon pattern to cover the bit line contact open region, and forming a junction region diffused to the silicon line pattern through the bit line contact open region. Thereby, a stacked structure of a titanium layer and a polysilicon layer are stably formed when forming a buried bit line and a bit line contact is formed using diffusion of the polysilicon layer to prevent leakage current.

Abstract: A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar.

Abstract: A data write circuit of a semiconductor apparatus includes a plurality of latches configured to latch a plurality of data in response to activation of a plurality of control signals and output the latched data to data lines; and a control unit configured to generate the plurality of control signals to be activated at different timings, such that partial data input at relatively earlier timing among the plurality of data is latched at earlier timing than the other data by a portion of the plurality of latches.

Abstract: A temperature sensing circuit includes a signal generation unit including a delay line and generating a source signal with a pulse width corresponding to a delay value of the delay line, a pulse width expansion unit configured to generate a comparison signal by expanding a pulse width of the source signal, and a change detection unit configured to sense a temperature change using a difference between the pulse widths of the comparison signal and a reference signal.

Abstract: A cache programming method for a non-volatile memory device includes programming data for a current programming operation into a memory cell array, determining whether the current programming operation has been performed to a threshold point of program completion, and receiving a data for a next programming operation when the current programming operation has been performed to the threshold point of program completion.

Abstract: A semiconductor device includes a storage node contact plug, a bit line in communication with to the storage node contact plug, and an expansion unit formed on a sidewall of the bit line. Thermal expansion of the expansion unit serves to increase capacitance by ensuring a distance between the bit line and the storage node contact plug, thereby improving a sensing margin. A cell characteristic such as a record recovery time (tWR) may be enhanced.

Abstract: A technology is a semiconductor cell and a semiconductor device capable of reducing the coupling capacitance between adjacent bit lines by forming a bit line junction region in a separated island shape when forming a buried bit line, thereby improving characteristics of the semiconductor devices. The semiconductor cell includes a transistor including a gate and a gate junction region, a plurality of buried bit lines disposed to intersect the gate, and a plurality of bit line junction regions, each bit line junction region having an island shape formed between the buried bit lines and connected to the buried bit line.

Abstract: A method of 4-bit MLC programming a nonvolatile memory device includes inputting an mth program operation command and sequentially executing first to fourth logical page program operations according to first to fourth logical page program start voltages, each stored in first to fourth logical page program start voltage storage units, wherein a program voltage, which is applied at a time point at which a memory cell programmed higher than a lowest verify voltage while a program operation of each logical page is performed occurs for a first time, is updated to each logical page program start voltage.

Abstract: A semiconductor memory device includes a plurality of repair fuse units configured to program repair target addresses respectively for repair target memory cells, wherein at least one of the repair fuse units is programmed with data information used for different purposes from the repair target addresses, a plurality of address comparison units each configured to compare an access target address with a corresponding address of the repair target addresses and determine whether to perform a repair operation or not, and a data transfer unit configured to transfer the data information to a corresponding circuit of the semiconductor memory device.

Abstract: The column address counter circuit of a semiconductor memory device includes at least one lower bit counter unit configured to generate a first bit of a column address by counting an internal clock, where the first bit is not a most significant bit of the column address, and a most significant counter unit configured to generate the most significant bit of the column address in response to a mask clock, where the mask clock is toggled when the internal clock is toggled by a set number of times.

Abstract: A nonvolatile memory device includes a number of page buffer groups each comprising a number of normal page buffers, I/O lines corresponding to the respective normal page buffers, and a column decoder generating a column address decoding signal for coupling the normal page buffers of one of the page buffer groups and the respective I/O lines in response to a normal control clock signal.

Abstract: A semiconductor memory device includes at least one first semiconductor chip including a plurality of memory cells and a second semiconductor chip including a fuse circuit configured to repair defective cells among the memory cells of the at least one first semiconductor chip.