Abstract: A method for allocating a channel at a BTS of an IMT-2000 system by using channel element information received from a call process block of a BSC (Base Station Controller) so as to allocate the channel element to the boards and to configure the allocated channel element information, is disclosed. The BTS includes a multi-user modulator (MUM), a multi-mode demodulator (MMD) and a combiner & channel decoder (CCD) boards. A storage area is generated to configure a linked list representing a relation between channel allocation information and each of the boards. The channel element allocation message is stored at the storage area and channel information is extracted from the stored channel element allocation message to analyze a sector ID of the channel element. A normal state of MUM, MMD and CCD boards are searched to allocate a channel at the searched MUM, MMD and CCD boards and rewrite the channel allocation information of the MUM, MMD and CCD boards.

Abstract: Metal layer in a semiconductor device and method for fabricating the same, the semiconductor device having a transistor and a capacitor electrode formed on a region of a semiconductor substrate, the metal layer including a planar protection film on an entire surface of the semiconductor substrate inclusive of the transistor and the capacitor electrode, an absorber layer over the planar protection film inclusive of a region over the transistor, an insulating film on an entire surface, with a width of projection in a relievo form in a region over the absorber layer, a via hole through the planar protection film and the insulating layer, to expose a region of the capacitor electrode, a tungsten plug and a planar stuffed layer in the via hole, a mirror metal layer on the insulating film on both sides of the projection of a relievo form of the insulating film, inclusive of the planar stuffed layer, and an insulating film spacer on the projection of a relievo form of the insulating film and the mirror metal layer i

Abstract: An apparatus for controlling a global positioning system (GPS) reference signal to be provided to a base station modem is disclosed to expand a coverage area of a base station, which comprises a GPS clock reception block for generating a system clock and a pp2s signal based on a reference time from the GPS; a system clock distribution block for distributing the system clock received from the clock reception block; a clock generation block for receiving the pp2s signal and generating a clock signal as base station synchronous signals for the expansion of the coverage area; a base station modem block with a multiplicity of base station modems, for performing data modulation/demodulation in synchronism with a corresponding clock signal; a CPU for generating a control signal; and a controller for allowing the data to be transmitted to a selected one among the base station modems, in response to the control signal.

Abstract: NAND type non-volatile ferroelectric memory cell and non-volatile ferroelectric memory of the same, in which numbers of access to a main cell and a reference cell are made the same, to maintain bitline induced voltages by the reference cell and by the main cell constant, for improving operation characteristics, minimizing a layout area, and permits a high density device integration, the memory cell including an N number of transistors connected in series, a bitline having an input terminal of a first transistor and an output terminal of (N)th transistor among the N number of transistors connected thereto, wordlines respectively connected to gates of the transistors except the (N)th transistor, a WEC signal line connected to a gate of the (N)th transistor and adapted to have an enable signal applied thereto only in a write or re-store mode, and ferroelectric capacitors respectively connected both to the wordlines and output terminals of the transistors.

Abstract: A computer simulation method for a semiconductor device manufacturing process, includes: a first step for forming an initial section of the material with only open cells exposed to the growth or etching among the cells; a second step for inputting information including growth or etching points into each open cell; a third step for computing a movement speed for the growth or etching points; a fourth step for moving the growth or etching points for a time determined according to the movement speed; and a fifth step for forming a new etching section by re-arranging the open cells exposed to the growth or etching, after moving the growth or etching points, the second to fifth steps being repeatedly performed on the re-arranged open cells until the sum of the predetermined time reaches the time (T).

Abstract: The present invention discloses a method for forming a bit line of a semiconductor device which can easily perform a contact process of the semiconductor device, by forming parallel rows of I-shaped active regions, a plug poly and a ladder-type bit line. The spacing between adjacent active regions is maintained at the minimum line width. Two word lines of minimum line width and separated by the minimum line width are formed on the active region. The word lines are perpendicular to the active regions. A plug poly is formed on the active region between the word lines. A bit line contact plug is formed over the plug poly and a device isolation region. A bit line of minimum line width contacts the bit line contact plug and aligned generally parallel to the word lines is formed in a ladder-type configuration. That is, one side the lower portion of the contact plug contacts the plug poly, and the upper portion of the other side of the contact plug contacts the bit line.

Abstract: The present invention discloses a mask set for compensating for a misalignment between the patterns and method of compensating for a misalignment between the patterns. A mask set of the present invention comprises a first mask consisted of a mask substrate on which a main pattern and a plurality of sub-patterns are formed, said sub-patterns formed at a side of the main pattern; a second mask consisted of a mask substrate on which a plurality of hole patterns are formed, the hole patterns corresponded to spaces between the main pattern and the sub-patterns of the first mask, respectively when the first and second mask are overlapped to each other; and a third mask consisted of mask substrate on which a plurality of bar patterns are formed, the bar patterns corresponded to the hole patterns of the second mask, respectively when the second and third mask are overlapped to each other.

Abstract: A semiconductor memory device includes a trench type SRAM(Static Random Access Memory) cell having a higher integration than a stack type SRAM. The SRAM cell memory device is provided with a trench formed in a semiconductor substrate and having four side walls therein, wherein a source and drain region of a drive transistor is formed in two of the four side walls, respectively, a pair of active layers respectively having a source and drain regions of a first load transistor is formed on the substrate adjacent to the side walls, and a gate electrode common to the load transistor is formed on a gate oxide film, whereby the gate electrode of the access transistor is vertically formed toward a direction vertical to the semiconductor substrate instead of being formed on the substrate for thereby decreasing an area to be occupied by transistor.

Abstract: A ferroelectric memory and method for fabricating the same includes a plurality of first gate electrodes and second gate electrodes formed on an active region of a substrate electrically separated form each other, a plurality of first electrodes of first ferroelectric capacitors each connected to the substrate at one side of the first gate electrode, and a plurality of first electrodes of the second ferroelectric capacitors each connected to the substrate at one side of the second gate electrode. Ferroelectric layers respectively formed on the first electrodes, and second electrodes are formed on the ferroelectric layers. A first metal line electrically couples the plurality of first gate electrodes, and a second metal line electrically couples the plurality of second gate electrodes. The ferroelectric memory has a simplified fabrication process and an increased area of the capacitor that is favorable for high density device packing.

Abstract: The CMOS image sensor includes a pixel array with M(row line)×N(column line) unit pixels, M and N being a positive integer, respectively, wherein each unit pixel includes a light sensing element, coupled to a sensing node, for receiving light from an object to generate photoelectric charges, a resetting unit, coupled to the sensing node, for making a fully depleted region within the light sensing unit and providing a reset voltage level to the sensing node in response to a first control signal, wherein the reset voltage level corresponds to a level of the first control signal and is supplied to a unit pixel of a next row line as a power source, arranged on the same column line, an amplifying unit for amplifying the voltage level of the sensing node to generate an amplified signal, wherein a power source of the amplifying unit is derived from a unit pixel of a previous row line, arranged on the same column line, and a switching unit, coupled between the amplifying unit and an output terminal, for perform

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, more particularly to a new dual gate P+ salicide forming technology having an elevated channel and a source/drain using the selective SiGe epi-silicon growth technology. It relates to manufacturing of a high performance surface channel PMOS salicide that has a number of beneficial effects.

Abstract: An image sensor according to the present invention can detect and correct an error value of a defective pixel. The image sensor includes an error detection circuit for detecting an error by comparing difference between a current pixel value and a previous pixel value with a predetermined reference value and an error correction circuit for correcting an error value from a pixel, by substituting the previous pixel value for the current pixel value.

Abstract: The present invention relates to a pinned photodiode for an image sensor and a method for manufacturing the same; and, more particularly, to a pinned photodiode of an image sensor fabricated by CMOS processes and a manufacturing method thereof The pinned photodiode, according to an embodiment of the present invention, includes a semiconductor layer of a first conductivity type; and at least two first doping regions of a second conductivity type alternately formed in the semiconductor layer and connected to each other at edges thereof so that the first doping regions have the same potential, wherein a plurality of PN junctions is formed in the semiconductor layer and the PN junctions improves a capturing capacity of photoelectric charges generated in the photodiode.

Abstract: A non-volatile memory device includes a floating gate formed over a semiconductor substrate. At one end of the floating gate, there is a tapered protrusion having a horn-like or bird's beak shape. A control gate covers the floating gate except for the tapered protrusion. Sidewall spacers are formed adjacent to the floating gate and the control gate. An erasing gate is formed over the tapered protrusion of the floating gate.

Abstract: A mobile telecommunication system for performing a handoff from an asynchronous communication system to a synchronous communication system includes: at least one asynchronous base station; at least one synchronous base station neighboring to the asynchronous base station, wherein the synchronous base station transmits channel signals; at least one dual-mode mobile station for selectively communicating with the synchronous base station and the asynchronous base station; and a reception unit, coupled to the asynchronous base station, for receiving and decoding the channel signals to transmit decoded signals to the asynchronous base station, wherein the asynchronous base station transmits the decoded signals to the dual-mode mobile station, thereby performing a handoff operation.

Abstract: An amplifier in a semiconductor integrated circuit includes a current-mirror typed differential amplifier and a cross-coupled differential amplifier, whereby a minute voltage difference from a bit line signal or a data bus signal is amplified. The amplifier for generating an amplified signal includes a load for coupling to a first voltage potential, a first sense amplifier responsive to a first data signal, and a second sense amplifier responsive to a second data signal. The first and second sense amplifiers are commonly coupled to the load, and the amplified signal of the first or second data signal is generated.

Abstract: Disclosed is a channel resource management method in a base station using a dynamic function in a mobile communication system, in which a real-time conversion of a traffic channel to an overhead channel using a dynamic function is allowed when a trouble occurs in the overhead channel of a base station of a mobile communication system adopting code division multiple access(CDMA) system like digital cellular system(DCS) or personal communication system (PCS), and normal servicing of terminal can be maintained by a minimum channel resource conversion resulted from an effective management of channel resource.

Abstract: The present invention provides a method for reducing or eliminating a poor pattern formation on a photoresist film by contacting the photoresist film with an alkaline solution prior to its exposure to light. Methods of the present invention significantly reduce or prevent T-topping and top-loss.

Abstract: A method and apparatus for forward and reverse power control in a mobile telecommunication system, wherein the transfer of power control data between a multi-mode demodulator board assembly and multi-user modulator board assembly installed in a base station is implemented on the basis of an independent power control bus, resulting in the occurrence of no time delay during the power control data transfer. Therefore, a mobile station is reduced in power loss, thereby enhancing the quality of speech.

Abstract: A semiconductor device for use in a memory cell includes an active matrix provided with a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate and conductive plugs electrically connected to the transistors, a number of bottom electrodes formed on top of the conductive plugs, composite films formed on the bottom electrodes and Al2O3 films formed on the composite films. In the device, the composite films are made of (Ta2O5)0.92(TiO2)0.08 by using an atomic layer deposition(ALD).