Abstract: A low power audio processor is disclosed which includes: a bit stream processing unit for performing bit processing for an applied audio stream and for decoding the bit processed audio stream to have a format conducive to digital signal processing; a digital signal processing unit for receiving the decoded data from the bit stream processing unit to perform digital signal processing; a post processing unit for post processing audio data from the digital signal processing unit to output final audio data; and a host interface unit for interfacing with an external device to provide an audio parallel stream from the external device to the bit stream processing unit.

Abstract: A power saving circuit for a liquid crystal panel (LCD) and a plasma display panel (PDP) recovers an energy charged in a panel capacitor through one path of a drive IC driving a scan electrode or data electrode for the PDP, and recovers the energy charged in the panel capacitor through one path of a column drive IC or row drive IC for the LCD panel. The energy recovery path can be a parasitic diode or protective diode of the drive IC. The power saving circuit can operate in an addressing period.

Abstract: A method for dynamically allocating a traffic channel element at an extended coverage of a base transceiver station which is divided by a cell site modem (CSM) ASIC in a mobile communication station is disclosed. In case that the call coverage is divided into a normal and an extended regions, the traffic channel element is not set to a pair of the normal and the extended channel elements. Instead, the channel allocation is dynamically allocated according to a channel type which is necessary on a call set up at each of the regions. The method reduces an unnecessary channel allocation and an occupation time of the channel elements, thereby enabling the capacity of the system to be increased.

Abstract: A semiconductor device isolation structure and a fabricating method therefor are disclosed. The isolation structure includes a trench which is formed on an isolating region to define an active region. First, second, and third insulating layers are deposited in the trench. The second insulating layer has an etch selection ratio different from those of the first and third insulating layers. The edge portions of the third insulating layer which contact the side walls of the trench characteristically do not show any collapse. Therefore, when supplying a subthreshold voltage, a hump phenomenon does not occur. As a result, leakage current is kept from increasing, and the device refresh characteristic can be kept from deteriorating. Further, the third insulating layer covers the top edge portions of the trench. Therefore, the gate insulating layer (which is formed later) has a sufficient thickness. Therefore, yield voltage characteristics can be kept from deteriorating.

Abstract: A method for forming silicon quantum dots and a method for fabricating a nonvolatile memory device using the same, suitable for high speed and high packing density. The method for forming silicon quantum dots includes the steps of forming a first insulating film on a semiconductor substrate, forming a plurality of nano-crystalline silicons on the first insulating film, forming a second insulating film on the first insulating film including the nano-crystalline silicons, partially etching the second insulating film and the nano-crystalline silicons, and oxidizing surfaces of the nano-crystalline silicons.

Abstract: This Rambus DRAM has a power save function which is not restricted in using time and has a short setting time, by forcibly compensating for a lost capacitor value in a memory cell to have a predetermined value, when a power save mode is changed to a normal mode.

Abstract: A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.

Abstract: A data processing method for a hybrid ARQ type II/III downlink of a wide-band radio communication system, wherein SRNC and CRNC are located on the same radio network, includes the steps of: a) generating RLC-PDU in a RLC layer of the SRNC and generating a PDU having RLC-PDU information needed for supporting the hybrid ARQ type II/III based on a header of the RLC-PDU (HARQ-RLC-Control-PDU); b) transmitting the RLC-PDU and the HARQ-RLC-Control-PDU to a MAC-D, treating a general user part of a MAC layer through a logical channel; c) transmitting the RLC-PDU and the HARQ-RLC-Control-PDU from the MAC-D to a MAC-C/SH, treating common/shared channel part of the MAC layer; d) transforming the PLC-PDU and the HARQ-RLC-Control-PDU to MAC-PDU and the HARQ-MAC-Control-PDU, respectively, in the MAC-C/SH, and allocating a format TFI1 of the MAC-PDU and TFI2 of the HARQ-MAC-Control-PDU, and transmitting the TFI1 and TFI2 to the MAC-D, and transmitting the MAC-PDU and the HARQ-MAC-Control-PDU to a physical layer of BTS, thro

Abstract: A mask set for measuring an overlapping error according to the invention comprises a first mask consisted of a mask substrate on which a plurality of unit patterns are formed. The plurality of unit patterns are arranged in radial shape round a given center. The mask set of the present invention further comprises a second mask consisted of a mask substrate on which a plurality of unit patterns are formed. The plurality of unit patterns of the second mask are arranged in same shape as the plurality of unit patterns of the first mask, whereby when the first and second masks are overlapped to each other, the unit pattern of the first mark and the neighboring unit pattern of the second mask maintains a certain angle.

Abstract: The present invention provides a CMOS (Complementary Metal Oxide Semiconductor) image sensor including a unit pixel, wherein the unit pixel includes photodiodes for receiving incident light and for generating photo charges, single sensing node for selectively receiving the photo charges outputted from the photodiodes; a reset transistor for resetting the single sensing node; and a drive transistor for outputting electrical signals corresponding to voltage levels of the single sensing node, and wherein the CMOS image sensor samples the electrical signals through the correlated double sampling and then outputs a final image value to an external device.

Abstract: A semiconductor device for use in a memory cell includes an active matrix provided with a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate and conductive plugs electrically connected to the transistors, a number of bottom electrodes formed on top of the conductive plugs, composite films formed on the bottom electrodes and A2O3 films formed on the composite films. In the device, the composite films are made of (Ta2O5)0.92 (TiO2)0.08 by using an atomic layer deposition (ALD).

Abstract: ESD protection circuit and method for fabricating the same, which has an improved performance, the method including the steps of (1) forming a transistor on a substrate, (2) forming a first insulating film on the substrate inclusive of the transistor and having a first contact hole to an input terminal of the transistor, (3) forming a buffered layer in the first contact hole and the first insulating film in the vicinity of the first contact hole, (4) forming a second insulating film on the first insulating film inclusive of the buffered layer and having a second contact hole to the buffered layer, and (5) forming a pad both on the second contact hole and the second insulating film in the vicinity of the second contact hole.

Abstract: A method for automatically controlling a semiconductor manufacturing process in a semiconductor factory, includes the steps of: a) receiving a lot specification data and a lot process data; b) comparing the lot specification data with the lot process data to determine whether a difference between the lot specification data and the lot process data is within a predetermined range; c) if a difference between the lot specification data and the lot process data exceeds or falls below a predetermined range, generating a first message representing an occurrence of an abnormally manufactured lot; d) generating a first transaction in response to the first message, the first transaction representing that the lot is abnormally manufactured; and e) storing the first transaction into a storage unit, so that a next lot process to the abnormally manufactured lot is prevented.

Abstract: The present invention relates to a pinned photodiode used in a CMOS image sensor. The pinned photodiode according to the present invention has an uneven surface for increasing an area of a PN junction of the photodiode. So, the increased PN junction area improves a light sensitivity of the photodiode. That is, the epitaxial layer, in which the photodiode is formed, has a trench or a protrusion. Also, in the pinned photodiode, since the P0 diffusion layer is directly in contact with the P-epi layer, the two P-type layers have the same potential and then it may operate in a low voltage.

Abstract: A TFT-LCD driver includes a TFT-LCD panel having a plurality of gate bus lines, a plurality of source bus lines, a plurality of TFT's, and a plurality of liquid crystal cells corresponding to the plurality of TFT's, a gate driver integrated circuit for supplying driving voltages to the gate bus lines to turn the TFT's on and off, a source driver integrated circuit for sequentially supplying analog voltages to the source bus lines so as to input the analog voltages to the plurality of liquid crystal cells through the turned-on TFT's, and a controller for providing control signals to the gate driver integrated circuit and the source driver integrated circuit, wherein the analog voltages supplied from the source driver integrated circuit to the TFT-LCD panel have the same polarity at least twice in sequence, wherein the source driver integrated circuit drives the TFT-LCD panel using one of a dot inversion method and a pixel inversion method.

Abstract: A method for manufacturing an aluminum oxide film for use in a semiconductor device, the method including the steps of preparing a semiconductor substrate and setting the semiconductor substrate in a reaction chamber, supplying an aluminum source material and NH3 gas into the reaction chamber simultaneously for being absorbed on the semiconductor substrate, discharging unreacted MTMA or by-product by flowing nitrogen gas into the reaction chamber or vacuum purging, supplying an oxygen source material into the reaction chamber for being absorbed on the semiconductor substrate, and discharging unreacted oxygen source or by-product by flowing nitrogen gas into the reaction chamber or vacuum purging.

Abstract: A semiconductor device for use in a memory cell including an active matrix provided with a silicon substrate, at least one transistor formed on the silicon substrate, a number of bottom electrodes formed over the transistors, a plurality of conductive plugs to electrically connect the bottom electrodes to the transistors, respectively, and an insulating layer formed around the conductive plugs. In the device, by carrying out a carbon treatment to top surface portions of the bottom electrode structure, it is possible to secure enough space to prevent the formation of bridges between the bottom electrodes.

Abstract: Solid state image sensor suitable for enhancing sensitivity of charge coupled devices (CCDs) using phase shift of light, and method for fabricating the same, the solid state image sensor including a plurality of photodiodes for generating image charges from incident lights, a plurality of charge coupled devices provided between the photodiodes for transmitting the image charges in one direction, a first flat layer formed on an entire surface of the photodiodes and the charge coupled devices, a plurality of color filter layers formed on the first flat layer to be in correspondence to the photodiodes, a plurality of black layers formed on the first flat layer between the color filter layers, a plurality of phase shift layers selectively formed on the color filter layers to be in correspondence to the photodiodes alternately, a second flat layer formed on an entire surface including the phase shift layers, and a plurality of microlenses formed on the second flat layer to be in correspondence to the photodiodes.

Abstract: A multistage interrupt controller provides a multistage storage means that processes external interrupt signals, including a plurality of multistage interrupt reception registers that can receive and provide temporary storage for corresponding external interrupt signals, an interrupt priority determining circuit that can receive the external interrupt signals from the multistage interrupt reception registers, determine priorities of the external interrupt signals, and dispose of the external interrupt signals according to the priorities, and a logical operator that inverts signals generated by the corresponding multistage interrupt reception registers and provides a logical feedback signal to the multistage interrupt reception registers.

Abstract: A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.