Abstract: The disclosed methodology and apparatus measure and correct the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds, thus providing a measured duty cycle.

Abstract: The disclosed methodology and apparatus measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit located “on-chip”, namely on an integrated circuit (IC) in which the DCM circuit is incorporated. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.

Abstract: The disclosed heterogeneous processor compresses information to more efficiently store the information in a system memory coupled to the processor. The heterogeneous processor includes a general purpose processor core coupled to one or more processor cores that exhibit an architecture different from the architecture of the general purpose processor core. In one embodiment, the processor dedicates a processor core other than the general purpose processor core to memory compression and decompression tasks. In another embodiment, system memory stores both compressed information and uncompressed information.

Abstract: Arrangements and methods for developing a software toolkit that can be used to design or obtain parameters for a sensor network. High-level guidelines on the basic relations between sensor network parameters like number of sensors, degree of quantization at each sensor, and the distortion requirements, based on a deep analysis on two basic coding possibilities (multiplexed point-to-point, distributed) are contemplated. By evaluating tradeoffs among the various parameters, an optimization framework to obtain the most cost-effective design with required quantization capabilities pertaining to given distortion criterion is provided.

Abstract: Streaming environments typically dictate incomplete or approximate algorithm execution, in order to cope with sudden surges in the data rate. Such limitations are even more accentuated in mobile environments (such as sensor networks) where computational and memory resources are typically limited. Introduced herein is a novel “resource adaptive” algorithm for spectrum and periodicity estimation on a continuous stream of data. The formulation is based on the derivation of a closed-form incremental computation of the spectrum, augmented by an intelligent load-shedding scheme that can adapt to available CPU resources. Experimentation indicates that the proposed technique can be a viable and resource efficient solution for real-time spectrum estimation.

Abstract: An object tilt and fall detection apparatus (30) capable of detecting the tilt and fall of an object by using a disk body (11) rolling according to the tilt of the object, comprising a timer means (50) starting the measurement of a time, stopping the measurement of the time by the rolling of the disk body (11), and displaying the time at which the measurement was stopped.

Abstract: An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a main array of storage cells and an auxiliary array of storage cells coupled thereto. When a particular row of the main array includes an instruction that is not ready-to-issue, a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row of the main array may bypass the row including the stalled or not-ready-to-issue instruction. To effect this bypass, the issue queue moves the ready-to-issue instruction to an issue row of the auxiliary array for issuance to an appropriate execution unit. Out-of-order issuance of instructions to the execution units thus continues despite the stalled instruction.

Abstract: This disclosure addresses providing gigabit-rate data transmission over wireless radio links, using carrier frequencies in the millimeter-wave range (>30 GHz). More specifically, a circuit for detection of amplitude-shift keyed (ASK) or other amplitude modulations (AM) which can be easily incorporated into an integrated circuit receiver system is described, making the receiver capable of supporting both complex IQ modulation schemes and simpler, non-coherent on-off or multiple-level keying signals. Several novel radio architectures are also described which, with the addition of a frequency discriminator network, have the capability of handling frequency shift keyed (FSK) or other frequency modulations (FM), as well as AM and complex IQ modulation schemes. These radio architectures support this wide variety of modulations by efficiently sharing detector hardware components.

Abstract: In the context of high-speed serial links, data-dependent jitter compensation techniques performed using phase pre-distortion. Broadly contemplated is an expansion of the notion of pre-emphasis beyond conventional amplitude compensation of ISI, whereby phase pre-emphasis for compensating data-dependent jitter (DDJ) is introduced. DDJ can be addressed by exploiting the relationship between the data sequence and the timing deviation. Phase pre-emphasis improves the signal integrity with little additional power consumption in the transmitter and with no cross-talk penalty.

Abstract: An information handling system including a divider circuit is disclosed that divides an input clock signal by a non integer value to generate an output clock signal. The resultant output clock signal exhibits a 50/50 duty cycle in one embodiment. The disclosed divider methodology permits the design of advanced circuit functions, such as double data rate memory operations, without the need for additional clock signal sources.

Abstract: A method and apparatus are disclosed for injecting errors in the functional units of a processor system, and for observing non-injected errors that occur in those functional units. A local error handler layer provides error injection for the various functional units at a local level. A global fault isolation register (FIR) layer couples to the local error handler layer to coordinate the handling of local errors in the multiple functional units of the processor system. A software debugger application or system software communicates with the global FIR layer to control error handling.

Abstract: A method and apparatus are disclosed for managing information in a collaborative design environment. A host zone includes host zone information handling systems (IHSs) that associate with a business entity such as an integrated circuit design and manufacturing house. The host zone IHSs store host zone confidential information. The method and apparatus also employs a partner zone including partner zone IHSs that associate with another business entities or entities, namely partners of the host business entity. A firewall couples the host zone to the partner zone in a manner which controls the flow of information between the host zone and the partner zone. In one embodiment, the disclosed method and apparatus protects personnel using the partner IHSs from exposure to host zone confidential information. In another embodiment, the disclosed technology permits a user of a host zone IHS to access information in the partner zone to assist the partner or partners with the collaborative design project.

Abstract: Methods and computer program products for accommodating unforeseen events using an electronic calendar. Occurrences of unforeseen events pertinent to preexisting appointments are detected. Occurrences of unforeseen events may be detected by, for example, accepting input from the user conveyed by, for example, a keyboard, a mouse click, or a menu selection; or by accepting input from an automated information source that provides, for example, commute times or weather reports. The calendar responds automatically on behalf of the user to the detection of unforeseen events pertinent to preexisting appointments. Response may include sending notifications to other parties to appointments by way of, for example, electronic mail, instant messaging, or voice mail messaging; by canceling appointments; or by rescheduling appointments.

Abstract: A system and method of enhancing a profile of a portable device. The system and method includes defining an event type in a scheduling tool and scheduling a time to initiate the event type. The system and method further includes associating a notification profile of a device with the defined event type and changing a setting of the device to the notification profile in response to the scheduling time and the defined event type.

Abstract: An apparatus and method providing flexibility to a silicon chip carrier which, in at least one embodiment, comprises multiple chips and a silicon chip carrier having thinned regions between some adjacent chips, thus, allowing for increased flexibility and reduced package warpage.

Abstract: A data initiator device designates an initial data tag set for tagging data transfers to thereby attach data tags from the designated set to commands directed to data transfers between the data initiator device and a data target device subsequent to the designation of the initial data tag set. The data transfer commands are issued with the attached data tags from the designated data tag set until an occurrence of a reset error associated with one of the issued data transfer commands. In response to the reset error, the data initiator device designates a different data tag set for tagging data transfers to thereby attach data tags from the newly designated data tag set to commands directed to data transfers between the data initiator device and the data target device subsequent to the designation of the new data tag set.

Abstract: Methods of forming low-k dielectric layers for use in the manufacture of semiconductor devices and fabricating semiconductor structures using the low-k dielectric material. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic state. The carbon nanostructures may be converted to the insulating electronic state either before or after a layer containing the carbon nanostructures is formed on a substrate. One approach for converting the carbon nanostructures to the insulating electronic state is fluorination.

Abstract: Systems and methods for the identification of correlated burst events among two or more data streams, given one or more specific query time spans are disclosed. Also broadly contemplated is the act of finding, from one or more data streams, those streams that have correlated burst events with another given data stream within a time span.

Abstract: The state or condition of a system may be evaluated by comparing a set of selected parameter values, converted into a trial vector, with a number of model or exemplar vectors, each of which was represents a particular state or condition of a sample system. Examples of such conditions may include “good”, “marginal”, “unacceptable”, “worn”, “defective”, or other general or specific conditions. Sets of parameter values from the system are converted into input vectors. Unprocessed vectors are then processed against the input vectors in an artificial neural network to generate the exemplar vectors. The exemplar vectors are stored in a memory of an operational system. During operation of the system, the trial vector is compared with the exemplar vectors. The exemplar vector which is closest to the trial vector represents a state which most closely represents the current state of the system.

Abstract: A method, system and program product accurately model the error characteristics of a communications system, such as a tape storage system. Input parameters are entered which describe defect rates and sizes, Codeword Data Structure bytes, and any interleaving factor. Bit defects from simulated defect sources are generated, defined by the starting and ending bits of each defect within a codeword. Any codewords which are defect-free are filtered out and not processed further, thereby increasing the processing speed of the model. Within the defect streams, overlapping defects are merged, redefining defect regions by starting and ending bits. Because only the definitions are processed, not the entire length of the codewords or defects, processing efficiency is further enhanced. The number of defects that occur in each codeword is determined and the probability of the occurrence of N bytes in error per processed codeword may be computed.