Abstract: A serial SCSI (SAS) storage drive system includes a drive enclosure having a first interface card coupled to one storage controller over a single SAS path and a second interface card coupled to another storage controller over a different single SAS path. At least one disk drive within the enclosure is assigned to the first storage controller and interconnected to the storage controller through the first interface card. At least a second disk drive within the enclosure is assigned to the second storage controller and interconnected to the storage controller through the second interface card. The interface cards are selectively interconnected with each other through a crossover port. In the event of a failure in a storage controller or an interface card, the crossover port may be activated, thereby maintaining access to both sets of disk drives.

Abstract: Resynchronization of data between a primary (production) data site and a secondary (recovery) site following a failure is enhanced when the size of a data track at the production site is different from the size of a data track at the recovery site. The recovery site reads an out-of-sync (OOS) bitmap created at the production site and expands or contracts the bitmap to accommodate the size difference. The resulting production site bitmap is merged with a OOS bitmap maintained at the recovery site to indicate those tracks which are to be transferred from the recovery site to the production site. Thus, only those tracks which are required to be transferred are transferred. Buffer space may be allocated in which to expand or contract the production site OOS bitmap. Buffer space may be conserved by sequentially reading portions of the production site OOS bitmap into a small buffer.

Abstract: A processor is disclosed that efficiently executes shift/rotate instructions. The processor determines if each shift/rotate instruction in an instruction stream is an immediate shift/rotate instruction or a register dependent shift/rotate instruction. If the processor determines that a particular shift/rotate instruction is an immediate shift/rotate instruction, then the processor sends the instruction to a shift/rotate functional unit for immediate execution. However, if the processor determines that a particular shift/rotate instruction is a register dependent shift/rotate instruction, then the processor breaks that instruction into two substitute instructions. A first substitute instruction loads a shift amount from a register file register into a shift amount register in the shift/rotate functional unit. A second substitute instruction performs a data shift specified by the data shift amount that the shift amount register stores.

Abstract: Ultra-thin oxynitride layers are formed utilizing low-pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, or a nitride layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or a single-wafer process chamber.

Abstract: Computer networks are provided with a resource efficient ability to generate link performance statistics. To calculate the average link utilization per I/O operation, a first counter accumulates the number of I/O operations processed by a link and a second counter accumulates the time required by the link to complete each I/O operation. The second value is then divided by the first value. The number of operations per second for a link may be computed by dividing the first number by a predetermined period of time and the average number of operations using the link may be computed by dividing the second number by the predetermined period of time. A third counter may be employed to accumulate the number of bytes transferred by a link during each I/O operation. Then, average size of an I/O operation may be computed by dividing the third number by the first number and the average bandwidth per link operation may be computed by dividing the third number by the predetermined period of time.

Abstract: A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.

Abstract: A method for initiating a data storage facility recovery process in a data processing system having a first peer data storage facility and a second peer data storage facility communicating with the first peer data storage facility by a communication link. The method of initiating a recovery process is invoked by one peer data storage facility upon another peer data storage facility operating under a peer to peer remote copy (PPRC) protocol. Data copied from a first peer data storage facility to a second peer data storage facility is monitored for errors. Upon detection of an error by one peer data storage facility, recovery and data collection operations are initiated on the other peer data storage facility. Preferably, the initiation of recovery and data collection operations occurs out of band, over a second communication link between the peer data storage facilities.

Abstract: An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.

Abstract: An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a matrix of storage cells configured in rows and columns including a first row that couples to execution units. Instructions advance toward issuance from row to row as unoccupied storage cells appear. Unoccupied cells appear when instructions advance toward the first row and upon issuance. When a particular row includes an instruction that is not ready-to-issue a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row may bypass the row including the stalled or not-ready-to-issue instruction. Out-of-order issuance of instructions to the execution units thus continues.

Abstract: In a fibre channel, arbitrated loop (FC-AL) network environment, an operating speed of devices within a switch domain within the network is optimized. The FC-AL switch domain is isolated from an attached storage controller, and a first signal is transmitted to each of a plurality of storage devices within the domain. The first signal comprises a request that each storage device transmit inquiry data to a control and management node (CMN) within the domain. In response to receipt of the inquiry data from each storage device, the speeds at which each storage device is operable are identified and an operational speed is then established for the domain. The established speed may be the fastest speed at which all devices can operate. Alternatively, one or more slower devices may be bypassed and the established speed may be the fastest speed at which all remaining devices can operate.

Abstract: A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.

Abstract: A method of recovery from a data storage system failure in a data storage system having a host computer writing data to a first storage unit with a first storage controller synchronously mirroring the data to a second storage unit, and with a second storage controller asynchronously mirroring the data to a third storage unit. Upon detection of an error or failure associated with the first storage unit, the synchronous data mirroring relationship between the first storage unit and the second storage unit is terminated and the host is directed to write data updates directly to the second storage unit. Upon correction of the failure associated the asynchronous mirroring of data updates from the second storage unit to the third storage unit is suspended and synchronous mirroring of the data updates in a reverse direction, from the second storage unit to the first storage unit, is commenced.

Abstract: An input device is disclosed, one embodiment of which provides position information to an information handling system (IHS). The position information includes both location information and spatial orientation information of the input device in real space. The input device includes a location sensor which determines the absolute location of the input device in x, y and z coordinates. The input device also includes a spatial orientation sensor that determines the spatial orientation of the input device in terms of yaw, pitch and roll. The input device further includes a processor that processes the location information and the spatial orientation information of the input device in real space to determine an image view from the perspective of the input device in virtual space. Movement of the input device in real space by a user causes a corresponding movement of an image view from the perspective of the input device in virtual space.

Abstract: In a data processing environment, data is replicated to a remote or secondary storage device in a manner which reduces the adverse performance effects and inefficient bandwidth usage imposed by the conventional one-transaction-at-a-time process. Transactions to be transferred are grouped by a replication manager by selecting transactions having start times earlier than the completion time of a first transaction. Thus, no transaction in a group will be dependent upon any other transaction in the group. Once selected, all transactions in the group may then be transferred to the secondary storage device.

Abstract: A mechanism for controlling the hardware resources on a blade server, and thereby limiting the power consumption of the blade server is disclosed. The enforceable hardware resources that are controlled include the base frequency of the central processing unit (CPU) as well as power to individual banks of physical memory, for example dual-inline memory modules (DIMMs). The hardware resources are tuned in dependence on actual server utilization such that applications running on the blade only have the allocated hardware resources available to them. Deactivated hardware resources are powered off and are so ‘hidden’ from the operating system when they are not required. In this manner, power consumption in the entire chassis can be managed such that all server blades can be powered on and operate at higher steady-state utilization. The utilization of the powered on resources in a blade center is also improved.

Abstract: A mechanism for changing ownership over the physical power to a blade server in a blade center chassis that prevents a malfunctioning blade from jeopardizing other components in the chassis. When the management module is not present, control over power to the blade is switched to a service processor on the blade. This arbitration of control over power to a blade is accomplished by implementing a watchdog timer mechanism. The management module is responsible for tickling the watchdog timer when the present in the chassis and operating normally. This mechanism provides the management module with control over power. If the management module malfunctions or is removed, control over power is switched to the local service processor on the blade server as soon as the watchdog timer is not tickled.

Abstract: A customizable cache discard policy is provided which reduces adverse consequences of conventional discard policies. In a data processing system, a cache controller invokes a cache data discard policy as the cache approaches its capacity. Using one possible policy, data having the shortest retrieval (fetch) time is discarded before data having longer retrieval times. In an alternative policy, data may be discarded based upon its source. Weightings may be applied based upon the distance from each source to the cache, may be based upon priorities assigned to each source, or may be based upon the type of each source.

Abstract: A method, apparatus and article of manufacture is provided for processing a previously encoded MPEG video high-resolution (HR) file and corresponding proxy file, for frame accurate timecode repair and synchronization of individual video frames of the HR and proxy files. Each video frame header of the HR and proxy files is modified by a compressed timecode packet having an identifying signature, an absolute timecode of the frame, and a relative timecode of the frame. The timecodes have the SMPTE timecode format HH:MM:SS:FF. The method automatically verifies the timecodes in the HR and proxy files timecode packets. If a repair of the HR file anomalous absolute timecodes is needed, the method automatically corrects the anomalous absolute timecodes in the HR file. If the proxy file starting video frame is offset from the HR file starting video frame, the method automatically synchronizes the proxy and the HR files absolute and relative timecodes.

Abstract: A glitch protect valid cell and method for maintaining a desired logic state value in response to a glitch signal and a timing signal. The glitch protect valid cell may be integrated with a content addressable memory (CAM) array for indicating whether word data stored within the CAM is valid. The glitch protect valid cell includes a memory element, a state machine, and a glitch protect circuit each responsive to one another. The glitch protect circuit includes a propagation delay assembly and a restore assembly electrically coupled to one another. The propagation delay assembly includes a first pull down network and a NOR gate electrically coupled to one another. The restore assembly includes a second pull down network electrically coupled to the propagation delay assembly. The first pull down network is responsive to the glitch signal and the timing signal to selectively engage the NOR gate.

Abstract: An automated data storage library accesses data stored on storage media contained in cartridges in response to commands from an external host. The cartridges include cartridge memory and a component in the library includes a cartridge memory interface for reading data from and/or writing data to the cartridge memory. When a cartridge is to be stored in the library, the library modifies the contents of the cartridge memory such that the data stored on the cartridge becomes inaccessible, thereby preventing access to the data outside of the library. To perform an authorized access, the library restores the contents of the cartridge memory or provides a correction or correction algorithm to allow access to the data without removing the access protection of the storage media. The cartridge memory may also or alternatively include an identifier which permits access to the data only by the identified physical and/or logical library(s).