Abstract: An apparatus is disclosed that surrounds a connector and places it within the printer body in such away as to allow for the connector to float against the intrusion of a sliding can mounted with electronics and to set up and enable the printer. The problem solved is that of the blind-mating connectors within a printer system for which an industry standard connector set for flex cable must be used. It is advantageous to allow a connector that is attached to a flex cable to float even though the floating feature has not been considered in the original design and the connector was not made for the amount of misalignment present in a blind-mate connection. In addition, by a single-rib design, an extra degree of freedom for rotational around Y-axis is provided to the floating connector to further guide the lead-in of the contacting face of the mating connector.

Abstract: The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.

Abstract: Memory Access Coloring provides architecture support that allows software to classify memory accesses into different congruence classes by specifying a color for each memory access operation. The color information is received and recorded by the underlying system with appropriate granularity. This allows hardware to monitor color-based cache monitoring information and provide such feedback to the software to enable various runtime optimizations. It also enables enforcement of different memory consistency models for memory regions with different colors at the same time.

Abstract: A data storage system and a method for managing a data storage system are provided. A storage controller is programmed with a disk configuration for each of one or more logical disk arrays and a protection level k. The available storage space from one or more disk drives in the data storage system is merged into a single virtual address space and the merged storage space is divided into storage segments. Next, the storage segments are allocated among the logical disk arrays and a configuration table is generated indicating the number of storage segments in each logical disk array and the physical location of each storage segment on a disk drive. The configuration table is stored in the storage controller and k copies of data may then be stored on the logical disk arrays. Multiple storage controller nodes may be accommodated to provide at least primary and secondary storage.

Abstract: A data storage system and a method for managing a data storage system are provided. A storage controller is programmed with a disk configuration for each of one or more logical disk arrays and a protection level k. The available storage space from one or more disk drives in the data storage system is merged into a single virtual address space and the merged storage space is divided into storage segments. Next, the storage segments are allocated among the logical disk arrays and a configuration table is generated indicating the number of storage segments in each logical disk array and the physical location of each storage segment on a disk drive. The configuration table is stored in the storage controller and k copies of data may then be stored on the logical disk arrays.

Abstract: Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads are able to share a cache, effective cache management is critical to overall performance. Color-based caching provides an effective method to better utilize caches and avoid unnecessary cache thrashing and pollution. Hardware maintains color-based counters relative to the cache lines to monitor and obtain feedback on cache line events. These counters are utilized for cache coherence transactions in multiple processor systems.

Abstract: A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from the power system exceeds a predetermined threshold power. The power system may reduce the rate of instruction issue by a particular core or clock gate a particular core to provide power throttling. The power system dynamically responds to variance of the actual output voltage that processor circuitry receives from the power system in comparison to an expected output voltage over time and corrects for such variance.

Abstract: A system, method and computer program product are provided to improve the efficiency of the transmission of consistency groups across multiple storage components by ensuring that volume transactions are evenly allocated among backup components. Each volume is initially assigned to a specified backup component. Once a color period begins, volume transactions are transmitted to the assigned backup component. Each backup component accumulates data transfer information for its assigned volumes throughout at least a portion of the color period and calculates a new volume assignment for the next color period. Before the start of the next color period, a captain storage controller transmits any new assignments to the backup components. During a next color period, the process is repeated using the new assignments.

Abstract: In one embodiment, the disclosed methodology and apparatus involves an integrated circuit that includes multiple interfaces. Each of the interfaces couples to a respective set of registers or storage elements on the integrated circuit. A bridge circuit on the integrated circuit switchably couples the two interfaces together such that one interface may communicate with the registers that associate with that interface as well as the registers that associate with the other interface.

Abstract: A system and method of managing networks and, more particularly, to a system and method for interfacing with virtual networking devices using SNMP (Simple Network Management Protocol). A system comprises a configuration statement configured to provide an identity to a virtual device. An SNMP subagent is configured to interface between an SNMP agent and a control program of the virtual device. The SNMP subagent acquires information extracted by the control program for the identified virtual device and provides the acquired information to the SNMP agent to be returned to the SNMP client.

Abstract: A method and system for recovering a server blade, in a multiple server blade computer, that is lost during a flash update operation on a service processor in the server blade. Because of the flash update failure, the lost server blade is unaware of its location on a management pathway, which in an exemplary form may be a midplane or a bus, which connects the server blade and a management module in a server blade chassis. The lost server blade puts a signal on the management pathway indicating that the flash failed. The signal is put on a special channel reserved for such messages. The management module receives the signal, and then determines which of the multiple server blades are lost due to the flash update failure.

Abstract: Within a group of components in a circuit, each component in the group has a thermal detector that describes whether that component is operating at a temperature that is normal, high or fatal. A first signal representing a first component's temperature is sent downstream to a second component in the group. If the second component is operating at the first component's temperature or lower, then the first signal is passed on downstream from the second component. However, if the second component is at a higher temperature, then the second component generates a second signal that represents the second component's temperature, and sends that second signal downstream. A signal representing the highest temperature detected in the group eventually reaches a master controller that, depending on the signal received from the group, lets the group continue to operate normally, throttles the group down, or else shuts the group down.

Abstract: Within a group of components in a circuit, each component in the group has a thermal detector that describes whether that component is operating at a temperature that is normal, high or fatal. A first signal representing a first component's temperature is sent downstream to a second component in the group. If the second component is operating at the first component's temperature or lower, then the first signal is passed on downstream from the second component. However, if the second component is at a higher temperature, then the second component generates a second signal that represents the second component's temperature, and sends that second signal downstream. A signal representing the highest temperature detected in the group eventually reaches a master controller that, depending on the signal received from the group, lets the group continue to operate normally, throttles the group down, or else shuts the group down.

Abstract: A system for recovering a server blade, in a multiple server blade computer, that is lost during a flash update operation on a service processor in the server blade. Because of the flash update failure, the lost server blade is unaware of its location on a management pathway, which in an exemplary form may be a midplane or a bus, which connects the server blade and a management module in a server blade chassis. The lost server blade puts a signal on the management pathway indicating that the flash failed. The signal is put on a special channel reserved for such messages. The management module receives the signal, and then determines which of the multiple server blades are lost due to the flash update failure.

Abstract: A computer program product is presented for recovering a server blade, in a multiple server blade computer, that is lost during a flash update operation on a service processor in the server blade. Because of the flash update failure, the lost server blade is unaware of its location on a management pathway, which in an exemplary form may be a midplane or a bus, which connects the server blade and a management module in a server blade chassis. The lost server blade puts a signal on the management pathway indicating that the flash failed. The signal is put on a special channel reserved for such messages. The management module receives the signal, and then determines which of the multiple server blades are lost due to the flash update failure.

Abstract: A tape drive and a method of using a tape drive is provided. The tape drive includes a head assembly including at least a first and a second servo read element configured to detect transition stripes of a servo pattern on tape media. The first servo read element is configured to detect at least two transition stripes of an even servo band on the tape media at a first time. The servo detection logic is configured to detect a timing of at least two transition stripes of the even servo band on the tape media. The servo controller is configured to position the head assembly laterally with respect to the tape media in response to the timing of the at least two transition stripes of the even servo band on the tape media. The second servo read element is configured to detect at least two transition stripes of an odd servo band on the tape media at a second time, wherein the second time is a time delay after the first time corresponding to a distance D.

Abstract: A method and a system are provided for writing a plurality of servo bands on magnetic tape. The magnetic tape is moved longitudinally relative to at least one servo write head. The servo write head is positioned to write a plurality of parallel longitudinal servo bands. The plurality of servo bands comprise odd servo bands and even servo bands, and each of the odd servo bands lie between the each of the even servo bands. The at least one servo write head is operated to write the plurality of parallel longitudinal servo bands on the magnetic tape such that each of the plurality of servo bands comprise a plurality of frames, wherein each frame comprises a plurality of bursts of transition stripes, and each burst has a first transition stripe.

Abstract: A magnetic tape cartridge including magnetic tape with servo information is provided. The servo information comprises a plurality of parallel longitudinal servo bands that lie between a plurality of longitudinal data bands. The plurality of servo bands include odd servo bands and even servo bands, wherein each of the odd servo bands lie between each of the even servo bands. Each of the plurality servo bands include a plurality of frames, wherein each frame includes a plurality of bursts of transition stripes, and each burst having a first transition stripe. The first transition stripe of each burst of each the odd servo band is longitudinally shifted from the first transition stripe of each burst of each even servo band by a substantially equal distance, D, such that servo information of the odd servo bands is interleaved with the servo information from the even servo bands.

Abstract: A receipt printer having a scissor cutter for cutting off a receipt from a paper roll. The scissor cutter includes a moving blade that articulates across an adjustable stationary blade. The adjustable stationary blade is adjustable laterally according to whether a full cut or a partial cut across the paper roll is desired. If a full cut is desired, the stationary blade is positioned against the full width of the paper roll. If a partial cut is desired, the stationary blade is positioned against only a portion of the width of the paper roll.

Abstract: In one embodiment, a test system tests a device under test (DUT). The DUT includes an internal test controller that executes built-in self-test (BIST programs. Built-in self-test programs include array-based automatic built-in self-test programs, discrete and combinational logic built-in self-test programs, and functional architecture verification programs (AVPs). An external manufacturing system test controller manages the internal test controller within the DUT and determines minimum operating voltage levels for a power supply input voltage that supplies the DUT. A logic simulator provides a modeling capability to further enhance the development of minimum voltage power supply input operational values for the DUT.