Abstract: A method for self-aligning an isolation structure to a diffusion region. A first masking layer is formed on a semiconductor substrate, the first masking layer having at least one aperture sidewall which is substantially perpendicular to the semiconductor substrate. Dopant ions are implanted into the semiconductor substrate through the first masking layer to form a doped region. Sidewall spacers are then defined on the sidewalls of the aperture, and a sidewall image reversal process is carried out such that the sidewall spacers define trench apertures in a masking structure. Finally, isolation trenches are etched into the semiconductor substrate through the masking structure. Alternatively, the implantation step is carried out after the sidewall spacers are defined on the first masking layer.

Abstract: A connector for lightwave guides with release levers attached at the narrow sides thereof, which, when lateral pressure is applied, actuate detents. Simultaneously at the narrow sides of the connector casing recesses are provided for the release levers such that the release levers do not rise more than a small amount above the edge of the recess; whereby, the connector can be pulled by manual actuation of the release lever through the recess.

Abstract: Attribute hierarchy system including hardware assisted by software for utilizing a stack structure of a multiple-level stack and a plurality of stacks for storing data and attributes. The stack structure provides that only the top of the stack is loaded and utilized. The software controls the hardware logic flow associated with the stack and the stacks. The hardware includes an attribute memory and character data storage, a character data counter and position register. An attribute mask and attribute processor control loading of the attributes. A command register pushes, pops or loads to the stacks along with a sequence controller input from the attribute processor. A command decoder determines sequence of operation for loading attributes and character into row buffers. A stack control flags when a valid load has occurred, and if no load occurred, the stack defaults and a copy operation occurs.

Abstract: An apparatus and method for monitoring the conductivity of a semiconductor wafer during the course of a polishing process. A polishing pad that contacts the wafer has an active electrode and at least one passive electrode, both of which are embedded in the polishing pad. A detecting device is connected to the active and passive electrodes for monitoring the current between the electrodes as the wafer is lapped by the polishing pad. The etch endpoint of the wafer is determined as a function of the magnitude of the current flow.

Abstract: A process and a device for substantially eliminating tolerance-dependent variations of a preselectable space between the components of an optical communication apparatus is described. U-shaped recesses are provided in a metal casing for pressing in flange-type necks of, for example, optical transmitting and receiving devices. The parallel arranged devices are so spaced from each other that they are not subject to tolerance-dependent variations. For this purpose the metallic necks are coated with a plastic layer, and ribs provided at the lateral walls of the U-shaped recesses dig into the plastic layer. The necks are pressed in precisely at a predetermined spacing by means of a gauge. By the application of varying degrees of pressure when the ribs are pressed in on one side and the other side of the neck, one of the U-shaped recesses can be off-center.

Abstract: A communication switching system in which control functions are distributed homogeneously, as opposed to being distributed by individual function, throughout the system. A plurality of controllers are coupled to a time division multiplex (TDM) bidirectional bus. Each controller includes a microprocessor to perform control functions. An interface element on the controller accesses the TDM bus while a switching element on each controller controls access between the interface element and the microprocessor. The switching element and interface element include storage areas which are double buffered to allow for more efficient operation and use of the memory space. The TDM bus is divided into a plurality of time slots. Each controller is assigned certain of the time slots and utilizes those time slots to communicate with other controllers. The system includes provisions for dynamic allocation of time slots.

Abstract: Apparatus is provided for testing a data processing system which includes a microprocessor, the testing occurring with the microprocessor in place in the system. The apparatus comprises: a support microprocessor for controlling the testing, a serial-to-parallel and parallel-to-serial converter connected between the support microprocessor and the system microprocessor, means for supplying a series of level sensitive scan design (LSSD) test signals from the support microprocessor through the converter to the system microprocessor, and means for returning the results of the level sensitive scan design test signals from the system microprocessor through the converter to the support microprocessor.

Abstract: A connection arrangement includes a plurality of sets of wiring planes, wherein any connection uses one and only one set of the planes. Each plane is a principal wiring direction. Various economies are affected by arranging the relationship between pairs of wiring planes in a set to have principal wiring directions lying at an acute angle. In one preferred embodiment each set includes a pair of planes and the acute angle between principal wiring directions is 45.degree..

Abstract: Diskette media and drive determination in which a diskette controller attempts to read the diskette according to a variety of formats having, for instance, different data transfer rates. A successful read is registered by the controller and that format is thereafter identified with the diskette drive and the diskette media inserted in the drive.

Abstract: A semiconductor photodetector is formed of interdigitated, metal-semiconductor-metal electrodes disposed on a surface of semi-insulating semiconductor material, gallium arsenide. Radiation such as infra-red or visible light is converted to an electric current flowing between the electrodes upon application of a bias voltage between the electrodes. A Schottky barrier at the junction of each electrode surface and the semiconductor surface limits current flow to that produced by photons of sufficient frequency, or energy, to overcome the Schottky barrier. Tunneling of charge carriers of the current under the Schottky barrier, which tunneling results from the entrapment of charge carriers on the semiconductor surface, is inhibited by the production of a doped surface layer upon the foregoing surface between the electrodes to repulse the charge carriers and prevent their entrapment at the surface.

Abstract: A compact optical scanner includes a base unit and a scan unit. The base unit includes an optical source such as a laser and an optical path directing a beam emitted by the laser to a scan mirror which is located in and supported by the scan unit. As the scan mirror rotates, the optical beam is reflected back to the base unit from which it is emitted as a beam scanning to and fro in a scan plane. The scan unit is supported by reference to the base unit such that the oscillation axis of the scan mirror is substantially and preferably parallel to the scan plane.

Abstract: A dynamic random access memory (DRAM) is comprised of a first and a second input/output (I/O) bus, a first and a second I/O sense amplifier, and a first and a second I/O bus precharge circuit. A control circuit is responsive to the state of a mode control signal for enabling the operation of the I/O buses and the precharge circuits such that in one mode of operation the DRAM operates in a conventional single bit per CAS cycle page mode. In a second mode of operation a high speed dual bit per CAS cycle page mode is achieved, wherein the I/O buses are alternately enabled, one being enabled when CAS is asserted and the other being enabled when CAS is deasserted. The dual bit mode of operation provides also for precharging the I/O bus which is not enabled during the period when the other bus is enabled.

Abstract: A circuit-switched local area network relies on a star topology for data transfer. Signalling information is confined to a single common signalling link or channel. Contention on the signalling link or channel is obviated by the use of a contention resolution device which is coupled to all ports for receiving requests to send from the ports and for providing clear to send messages to the requesting ports, in turn. A port desiring communication with another port first raises its request to send and when it receives a clear to send from the contention resolution device, it places the message or call set up information on the signalling link or channel. Once the call or message set up information has been transmitted, the addressing port may de-assert its request to send which will result in the contention resolution device de-asserting the clear to send.

Abstract: By examining parity for a bit combination representing the present phase state of a stepping motor, a selection can be made as to which phase state should be changed in order to produce rotation of the step motor in a predetermined direction. By including within the parity determination not only the present phase state of the stepping motor, but the logic level of a direction bit (DIR), appropriate phase sequence for either CW or CCW rotation can be selected. In a hardware embodiment of the invention, a conventional parity generator module is used with inputs representing the present motor phase states as well as a logic level for a DIR bit. The output of the parity generator then determines which phase state to change to produce the desired rotation. In a software embodiment, a digital computer dedicates a phase state byte with a bit from each motor phase state and an additional DIR bit. Parity can be determined using a conditional branch on parity instruction or merely summing the phase direction byte.

Abstract: An automated assembly facility includes a random storage facility for each assembly line conveyor and associated series of assembly stations. The assembly line conveyor is located between the random storage facility and the series of assembly stations. A first conveyor is coupled between plural sources of carriers and the random storage facility. The random storage facility is coupled to the assembly stations by a transfer conveyor so that carriers can be transferred directly from random storage to an appropriate assembly station, obviating the need for the assembly line conveyor to cooperate in this transfer. The layout leaves the assembly station accessible from three sides. Efficient space use is achieved by providing one access aisle for each pair of assembly lines; random storage facilities of two lines are directly adjacent each other.

Abstract: Adjacent lying plug-connector halves, the front ends of which exhibit pin or sleeve shaped plug elements, are provided with first and second supporting bodies, of which the first supporting body, with a sleeve shaped plug element, may be connected by means of a joinable groove-tenon-interconnect lying crosswise to the plug insertion direction, and exhibits an entrance channel for a plug connector half with a pin shaped plug element. The second supporting body with a concentric guiding tube for the insertion of pin shaped plug elements from both directions exhibits a tenon-groove-interlock contour at both ends that matches that of a sleeve shaped plug element. The first supporting body can therefore be interlocked with second supporting bodies or sleeve shaped plug elements at choice, whereby light wave guides single or double plugs may be connected to transmit- and/or receive modules and light wave guides single or double plugs may be inter-connected.

Abstract: A robotic system includes two joints moving a common load-bearing member along a path for positioning a load. Each joint includes a linear electric motor and a feedback loop, the latter driving the motor accurately in response to a commanded position signal, and a true position signal provided by sensor apparatus disposed alongside a track of each linear motor. Cross-coupling circuitry connects with the sensor apparatus of each joint to produce signals representing differences in positional error and in speed of the joints. The signals are injected into the feedback loops of the joints to effect a shift of power between the joints to synchronize their travel. Window comparator circuitry is employed for introduction of variable gains to the feedback loops for values of positional error and velocity which are greater than reference values in a window.

Abstract: A process for laminating discrete sections of a supported photosensitive layer onto a continuing series of sheet substrates. Each substrate is advanced to and through the nip of heated application rolls, and a continuous length of the supported photosensitive layer is also supplied to the nip. When the substrate reaches a first location positioned between the application rolls, all movement ceases except that the rolls move from an inactive disengaged position toward the substrate to an active position to cause pressure contact between the photosensitive layer and the substrate to thereby laminate the photosensitive layer to the substrate. There is a pause for a predetermined period of time with the rolls in the active positions before the substrate is again advanced with the rolls still in the active positions and the photosensitive layer again supplied to the nip.

Abstract: A switching system or local area network is non-blocking, transmit-secure and employs a star type topology. A back plane uses n(n-1) bus lines to interconnect n ports. Each port can transmit on any one of n-1 bus lines depending on the identity of the destination port. Likewise, each port can receive from any of n-1 bus lines, depending on the identity of the transmitting port. Signalling as well as data flow on the same bus lines. Each of the ports includes a dedicated microprocessor along with an arbitrator to resolve contention. The ports further have transmit and receive multiplexers coupled between the back plane and an associated work station or information source/sink.

Abstract: For step motors positioned in response to an external reference location, correction for potential one step misalignment is provided. The method and the apparatus of the invention provide a read/write memory, for storing therein a phase state of the step motor at a particular location, e.g. a home position. The home position may coincide with the external reference location or may be offset therefrom by some predetermined move of the step motor. During cold starts, where memory is not retained, the step motor is moved to its home position and then the phase state of the machine is saved. On subsequent warm starts, after the step motor is moved to the assumed home position, the step motor is controlled to assume the phase state that has been previously stored.