Abstract: The high resistance of diffused electrical interconnection lines used for ground return paths in MOS field effect transistor (MOSFET) arrays limits their size and performance. Advantage is taken of the extra interconnection level available from conventional double-layer-polycrystalline silicon (polysilicon) processes to distribute ground potential to arrays, by means of a polycrystalline grid with direct contact to diffused electrodes therein, thus greatly reducing the deleterious effects of ground resistance. The proposed ground grid is integrated into the structure of a MOSFET ROM using a typical double polysilicon process. The first polysilicon level provides the conductive medium for said ground grid and the diffusing doping impurities that form contiguous source electrodes for the array MOSFETs. Gate electrodes thereof and word lines are formed out of the second polysilicon level. Drain electrodes are diffused and contacted by metallized output lines.

Abstract: An X-Y positioning system for electron beam lithography employs an adaptive drive system for feedback control. A gradually increasing drive voltage, superimposed upon a step wave, is summed with the position error signal to achieve position within the system deadband zone. The drive voltage, while superimposed upon the error voltage, increases until mechanical friction and drift in the deadband zone are overcome. A function generator alters the error signal such that the combined error signal and drive voltage cause the system to approach the null point minimizing servo oscillations. A limit circuit determines when the system has reached a set of inner limits and generates an operative output signal to the signal controller which continues until the position exceeds a second, outer set of limits.

Abstract: An FET transmission logic parity circuit is disclosed which determines the odd or even status of register bits using zero DC current transmission logic. The circuit has a first two FET devices which propagate the state of the preceding odd or even nodes and the corresponding register bit is logically a zero. A second pair of FET devices switch the state of the odd or even nodes when the corresponding register bit is logically a one. In this manner, the output nodes are statically conditioned to either a first potential or a second potential, depending upon the register bit states and no DC current flows between the first and second potential.

Abstract: A control unit for a functional processor is disclosed which minimizes programming complexity by eliminating data transfers and the transfer control associated with two level memory systems and which improves flexibility in program task changeovers in pipelined arithmetic architectures. This is accomplished by employing common page addressing for accessing memory address stacks for storing either main memory addresses or address increments, coefficient address stacks for storing coefficient memory addresses or address increments, and microinstruction sequencing control branch stacks for storing branch and loop control parameters. This permits chaining of long sequences of signal processing subroutines without external control and the associated execution time overhead.

Abstract: A method and apparatus for detecting defects in apertures plates such as masks. The plate is illuminated by a collimated light beam and defects or irregularities are signalled by a bright spot of light. A modified microfilm reader or the like can be used to magnify and project an image of that portion of the plate associated with the bright spot of light.

Abstract: A highly conductive layer utilizing a layer of Pt in conjunction with sputter deposited or co-evaporated WSi.sub.2 to enhance the conductivity increase of the WSi.sub.2 layer occuring during annealing. The Pt layer is deposited as a thin layer directly on top or beneath the WSi.sub.2 layer or may be incorporated within the WSi.sub.2 layer. During annealing platinum atoms diffuse into the WSi.sub.2 film resulting in lower resistivity values than in comparably deposited annealed film wherein the Pt layer has been omitted.

Abstract: A 3.58 MHz subcarrier signal and a 14.318 MHz clock signal are applied to three flipflops (50, 52 and 54) in such a manner that there appears on the output terminals (Q and Q) of the latches individual phase-shifted subcarriers having relative phases of 0.degree., 180.degree., 90.degree., 270.degree., 135.degree. and 315.degree. , respectively, representing the colors yellow, blue, red, cyan, magenta and green, respectively. Computer-generated digital color signals (+BLUE, +GREEN, +RED) are applied to the switching inputs (A, B, C) of a multiplexer (56) in order selectively to switch to the output of the multiplexer individual ones of the phase-shifted subcarriers in accordance with the code represented by the digital color signals. The individual subcarriers are combined in a summing circuit (62, 64) with television synchronizing and blanking pulses to produce a composite video color signal which is directly compatible with a conventional composite monitor and, after R.F.

Abstract: A low capacitance pad structure is disclosed for testing a semiconductor chip, so as to enable the accurate measurement of rise times and delays in internal logic circuitry. The structure provides a capacitive coupling between the internal logic circuit under test and the capacitance of the probe connected to the input/output pad of the chip. This is achieved by inserting a coupling capacitance between the internal logic circuit and the input/output pad. The coupling capacitance is formed by providing a thin dielectric layer on top of an enlarged plate portion of the conductor line connected to the output of the internal logic circuit under test, so as to capacitively couple voltage swings on the line to a second level plate which forms the electrode to be contacted by the test probe.

Abstract: A decoupling capacitor for mounting on an integrated circuit multi-layer ceramic. A bottom layer electrode, is evaporated or sputtered onto a carrier. A high dielectric layer is deposited followed by the upper metallurgy and a top isolating layer. Via holes are etched to respective electrode layers, BLM deposited thereon followed by solder balls. The electrode is mounted onto the substrate, solder balls face down in contact with a compatible footprint.

Abstract: A DC arc suppression circuit is disclosed for suppressing arcs which occur across a mechanical switch or circuit breaker. Several embodiments are described which employ a bipolar transistor to actively shunt the load current around the mechanical switch when the contacts are opened for a period of time long enough to enable the contacts to be separated by a sufficient distance to prevent arcing. Arcing is prevented when contact bounce occurs upon closure of the contacts, by providing a diode connected in parallel with the base-emitter portion of the circuit which restores the arc suppressing capacity of the circuit almost immediately upon the first closure of the contacts.

Abstract: A self-switched in-band signaling communication apparatus is disclosed which enables the switching of the signaling mode to the data mode on a single transmission line between a data terminal equipment or data communication equipment and the data port of a satellite communications controller, and the opposite switching from the data mode to the signaling mode under a single control bit. Signaling to and from the data port of the satellite communications controller is carried out using conventional dialing pulses at a signaling rate which is independent of the line data rate. The apparatus provides for the multipoint communication between a plurality of data terminal equipments using a unique multipoint turn-around process which provides a mobile bandwidth capability for the communications system.

Abstract: Image transferring apparatus for a continuously variable reduction electrostatic copier. A single fixed aperture is employed, adjacent the object plane, to:(1) reduce image intensity variations caused by non-uniform illumination across the object plane;(2) correct for lens cos.sup.4 losses for one mode of reduction;(3) reduce image distortions due to photoconductor drum curvature, particularly at edges; and(4) reduce image illuminance variations due to changes in reduction mode throughout a continuous range of reduction modes.In accordance with preferred embodiments, the foregoing functions are achieved notwithstanding movement in image or optical center line as a function of reduction to compensate for corner referencing objects to be copied. The single fixed aperture provides for adequate reduction in intensity variations, i.e.

Abstract: An FET driver circuit is disclosed which provides short circuit protection at the output node without reducing its performance. Grounded short circuit protection is achieved by sharing a load resistance at the output node in two parallel components, a low resistance active FET load and a high resistance active FET load. A delay element is inserted between the data input node and the gate for the low resistance active FET load. When the data input is low, both of the active FET load devices are off and the active logical FET device is on causing a low output value for the circuit. When the data input for the circuit goes high, the output capacitance is initially charged by the high resistance FET load device and is followed after a short delay, by charging through the low resistance FET load device. The low resistance FET load device cuts off current flow automatically after a predetermined period of time transpires.

Abstract: In a TDMA satellite communications system, the data ports at two different earth stations have their data rates synchronized. The origination port stores the last eight-bit byte of data in each 480-bit packet which is transmitted via the satellite. The last byte is compared with each of the 60 bytes of data in the next channel's worth of information received from the terrestrial source. If all of the bytes of data in the new channel's worth of information are identical to the last byte of data transmitted from the originating port, no information is transmitted for this data port in the next TDMA frame. The synchronized data port at the receiving earth station expects a channel's worth of data to be received during the next TDMA frame. The last byte of received data for the recipient data port in the last frame is stored.

Abstract: An asymmetric RAM cell is disclosed which will have a predictable initial storage state when pulsed drain voltage is turned on and yet after the initial turn-on interval, will operate in a symmetric fashion storing either binary ones or zeros. Thus, an initial prestored set of information can be permanently provided in a memory array made up of such cells, by orienting each individual cell at the time of manufacture so as to selectively represent either a binary one or zero. This is illustrated in the FIGURE where the upper cell has a first state by virtue of its orientation and the lower cell has a second, opposite state by virtue of its relative opposite orientation. When the array is turned on, the upper cell will have the opposite binary state from the lower cell. Thereafter, each cell can be respectively switched for storing ones and zeros in a normal RAM operating mode.

Abstract: An encryption system is disclosed which is based on channel destination addresses for a time division multiple access (TDMA) satellite communications network. A superframe initialization vector is transmitted from a master station to all other stations in the network. A plurality of frame initialization vectors is sequentially generated at each station in an encryption engine, from the superframe initialization vector, using a key which is common only to authorized users within the network. Each data channel is initialized with encryption bits produced by exclusive ORing the channel destination address and the frame initialization vector for the frame in which that channel is to be transmitted, and then passing the output of the exclusive OR through the encryption engine using either the same key or a second, different key. These encryption bits are combined with the channel data in an exclusive OR circuit for TDMA transmission via the satellite transponder to the receiving stations.

Abstract: A vertical PNP bipolar transistor structure with Schottky Barrier diode emitter is disclosed which simplifies the structure and process steps for combining a complementary PNP in an NPN integrated circuit and improves the speed and density of the vertical PNP. The PNP emitter is formed with a Schottky contact such that only the PNP base region is contained in the NPN emitter junction structure. The structure uses a separately masked ion/implant for the NPN intrinsic base implant which also forms the PNP collector region so that the PNP base doping profile can intercept the PNP collector profile at a lower concentration resulting in lower collector/base capacitance, lower series collector resistance and higher collector/base breakdown voltage for the PNP. Since the base doping concentration is lower in the structure and the emitter has no sidewall capacitance, the PNP emitter-base capacitance is greatly reduced. These features result in an improved frequency response for the PNP structure.

Abstract: A fully selectable static memory cell formed in a single isolation region comprises a pair of word lines, an SCR latch including an NPN device and an associated parasitic PNP device connected between the word lines, and a pair of bit lines, each of which is connected to the NPN device and the PNP device either directly or through a Schottky diode or an additional transistor device.

Abstract: Fine alignment of mask and wafer, using Fresnel zone plates is achieved. Light is focused on the wafer by a zone plate in the mask. Light diffracted from a zone plate on the wafer is received by a sensor. The received light is coded (analog or digital) to indicate alignment. For analog coding the wafer zone plate diffracts light to the sensor from an area of the wafer zone plate which is indicative of alignment. For digital coding, the wafer zone plate is digitally encoded as a function of alignment to similarly code the diffracted light. To eliminate ambiguity, the mask zone plate is formed from a plurality of "elements", each of which is itself a Fresnel zone plate. The focal length of the elemental Fresnel zone plate can be related to the mask/wafer separation distance, whereas the focal length of the macro zone plate (made up of a plurality of the elemental zone plates) is related to the distance between mask and light sensor.

Abstract: A fabrication process for a gallium arsenide MESFET device is disclosed. A feature of the invention is placing a gate structure on the gallium arsenide substrate. Then a process including molecular beam epitaxy, grows epitaxial gallium arsenide on each respective side of the gate, forming a raised source region and a raised drain region. Gallium arsenide will not grow in a conductive state on top of a tungsten gate metal. The resulting MESFET device has a raised source and drain which significantly reduces the high resistance depleted surface adjacent to the gate which generally occurs in planer gallium arsenide MESFET devices. Furthermore, the MESFET channel region which is defined by the proximate edges of the source and the drain, is self-aligned with the edges of the gate by virtue of the insitu process for the formation of the source and drain, as described above.