Abstract: A process for etching deep trenches to achieve dielectric isolation for integrated circuit devices; the process insures obtaining substantially perfectly vertical trench walls by precluding significant variation in etch bias during the trench formation.

Abstract: Disclosed is a means for enhancing logic circuit performance and more particularly, for enhancing the switching speeds of a variety of logic circuits. What is involved is the insertion of a so called "snap" or enhancement transistor connected to a common node defining an output of a basic logic circuit. In one example, the emitter of this "snap" transistor is connected to an output node in the circuit, which in conventional practice would be charged during an upgoing transition by a fixed RC time constant. In accordance with the present improvement, however, the "snap" transistor, due to charge stored therein, remains conducting--although the associated logic device is turned off. This current discharges as reverse base current and the output provides what appears to be an inductive voltage spike. The effect is that a temporary source of current is available to charge the common node.

Abstract: A reactive ion etching technique is disclosed for etching a gate electrode out of layers of tungsten silicide and polycrystalline silicon without etching the underlying layer of silicon dioxide which serves as the gate dielectric and which covers the source and drain regions. The key feature of the invention, wherein the gate, which has been partially etched out of the tungsten silicide and polycrystalline silicon layers, is coated with poly tetra-fluoroethylene (teflon) to protect the sidewalls of the gate from being excessively etched in the lateral direction while the etching continues at the bottom on either side of the gate.The process is especially suitable for formation of tungsten silicide structures since no subsequent thermal steps are required which would otherwise cause a delamination of the tungsten silicide.

Abstract: A "natural" threshold device is serially connected between the gate of an output depletion mode FET device and the input node to an FET device so as to provide current flow from the input node to the gate of the FET device as the input waveform begins to rise, and yet to provide sufficient resistance in the gate circuit of the depletion mode device so as to prevent backward flow of current from the gate as the potential of the output node rises. This increases the conductivity of the output load device, thereby providing a faster rise time for the output waveform.

Abstract: A high density electronic circuit module which includes a thin flexible film chip carrier having circuitry on both sides thereof. The double-sided thin, flexible circuitry is fabricated by depositing a first layer of chrome-copper-chrome circuitry on an aluminum substrate. This first layer of chrone-copper-chrome circuitry is covered with a layer of polyimide. Vias are etched into the polyimide. Next, a second layer of chrome-copper-chrome circuitry is deposited on top of the polyimide. The first and second layers of circuitry are connected through the etched vias. Finally, hydrochloric acid is utilized to etch away the aluminum substrate carrier. It is noted that hydrochloric acid etches aluminum whereas it does not etch chrome-copper-chrome circuitry.

Abstract: Apparatus and method for measuring the signals from a transducer. The signals are processed to form a differential component normalized by a summation component such that common changes to the sensors response characteristic are compensated. The sensors performance at the limits of the sensing range is also improved by the summation signal.

Abstract: Synchronization can be acquired between a transmitting node and a receiving node on a time division multiple access communication link without the necessity for additional data bits in the data stream, by correlating the number of errors detected in any interval as revealed by the forward error correction field. Both synchronization bits and stuffing bits can be located without using any external frame timing information. Substantial bandwidth savings is achieved by the technique, which can be applied for arbitrary combinations of the number of input ports, the number of data bits per group, and the number of parity bits generated per group.

Abstract: A method and apparatus are disclosed for conducting broadcast, multipoint, and conference communications in a TDMA network at various data rates while simultaneously conducting point-to-point communications at other data rates, either between local ports or between geographically remote ports during time intervals within a TDMA burst, which are not necessarily predefined. The disclosed apparatus appends a direct destination address to each point-to-point port communication for transmission over a communications link, to directly address the intended destination port. The disclosed invention appends an indirect destination address to each broadcast communication transmitted over the communications link. A broadcast memory is provided at the receiving end of the communications link, for storing correlated direct addresses which are accessed by the indirect destination addresses, to directly address a plurality of intended destination ports.

Abstract: An interrupt processor is disclosed for an instruction pipelined digital processor, which includes an instruction classification system with a logic class decoder, a multistage, pipelined, interruptible-sequence detector, a multistage variable-return-address generator, and an active instruction completion, suppression, and termination control, to enable interrupting a sequence of instructions which execute out-of-order in the pipelined and digital processor, and to enable allowing a subsequent return to the interrupted program to resume processing of that program without error.

Abstract: A word processor supports two display modes, one unformatted mode comprising display of a partial page and another formatted mode displaying format of an entire page of text. Both modes impose minimal burden on the display allowing use, for example, of standard display chips with a variety of monitors including a standard TV set or TV monitor. Other advanced functions include simple addition, movement and deletion of text units or blocks; simplified underscore, underscore deletion, word underscore and word underscore deletion; and an uncluttered insert display regardless of the extent of inserted text. The hyphenate function is improved by informing the operator, via the display, of the relation between, not only the right margin and the hyphenate candidate, but also the relation between the hyphenate candidate and the actual preceding line endings.

Abstract: A pipelined charge coupled analog to digital converter which provides a plurality of serially arranged pipelined stages that are connected to pass signal and reference charge packets from stage to stage in a serial progression. The pipelined analog to digital converter includes one stage for each bit desired in the output bit stream, and thus, an analog to digital converter providing an n bit digital word corresponding to the input analog signal charge, includes n stages. While the time necessary to perform the analog to digital conversion is the sum of operating times of all the stages, because the converter is pipelined, each successive n bit digital word representing a different successive charge packet is produced succeeding a preceding digital word representing a preceding signal charge packet, by a delay equal to the processing time of only a single stage.

Abstract: Level sensitive scan design (LSSD) scan strings on an integrated digital logic circuit chip are employed for multiple functions of providing control parameters to logic blocks on the integrated circuit chip, and for providing reconfiguration messages to reconfiguration logic on the integrated circuit chip, in addition to the normal function of transferring test data to various portions of the integrated circuit chip. This reduces the number of input/output pads on the integrated circuit chip which must be dedicated to these functions.

Abstract: A combined read-only storage (ROS) and read/write random access memory (RAM) integrated circuit memory cell is disclosed. In a first cell embodiment, a ROS FET device and a RAM FET device are connected in common to a bit sensing line connected to a sense amplifier which senses if the ROS FET device has discharged the bit sensing line indicating that a gate is present on the ROS FET device. A write driver circuit is also connected to the bit sensing line, for providing current through the RAM FET device to the charge storage element for writing a one or a zero therein. In a second cell embodiment, a combined two-bit read-only storage and one-bit read/write random access memory integrated circuit cell is disclosed. The bit sensing line is shared by two ROS FET devices and one RAM FET device. In a third cell embodiment of the invention, a single binary bit is stored for read-only storage and a single binary bit is stored for read/write random access memory storage.

Abstract: A miniature variable drive pin projection mechanism is disclosed for driving a conveyer belt to transport semiconductor chips from a test point to a sequence of sorting locations. The drive wheel is mounted to an indexing shaft which is sequentially rotated in a start and stop mode. The wheel has spring-loaded pins which are radially mounted in the wheel and are spring-loaded so as to be withdrawn from the peripheral surface of the wheel. Drive means are provided to actuate the pins during only 60 degree rotation of the wheel. During the remainder of 300 degree rotation of the wheel, there is substantially frictionless engagement.The resultant mechanism significantly reduces wear, vibration and misregistration of the assembly and lengthens its operating life.

Abstract: A cross-coupled, latch-type clock driver circuit is disclosed which enables the carrying out of level sensitive scan design (LSSD) testing. During normal operation, the circuit functions to prevent a pair of input clock waveforms from overlapping. This is achieved by applying a low state to a control signal input which causes the circuit to perform a latching operation on the input clock waveforms by providing a conductive cross-coupled connection between a first and second NOR Logic elements connected to the input clock waveforms. Then the outputs of the NOR elements will be insured to be nonoverlapping. During the test mode, the input clock waveforms must not be latched, in order for LSSD testing to be carried out. This is achieved by applying a high state to the control signal input, which disables the cross-coupled connection between the NOR logic elements. The circuit then becomes transparent to the input clock waveforms, enabling testing operations to be performed.

Abstract: A testing technique is disclosed for assuring AC performance of high speed random logic, employing a low speed tester. AC testing on a low speed tester is split into multiple phases. During the first phase, a slack time delta is introduced, which is the time difference between the product cycle time required by the application and the tester cycle time used in the product test. The product is tested with this timing using conventionally generated test patterns. The effect of the slack is then resolved in the subsequent phases of the test. The product is tested again with the same type test patterns as in the first phase, but with redefined strobe times at the staging latches in the circuit. The slack delta is transferred to paths between the consecutive staging latches and the resultant signals arrive and get sampled by the low speed tester as if there were no slack.

Abstract: A digital adder circuit is disclosed which employs non-DC current configurations to significantly reduce power, device count, and delay in performing binary addition. The circuit features a carry propagate transfer FET device whose gate is controlled by a carry propagate control circuit which selectively gates on the transfer FET device at a particular adder bit stage when the carry-in binary bit is to be transferred as the carry-out binary bit, which takes place when the augend input bit and addend input bit at that stage are not equal. The circuit additionally features a carry generate control circuit which is connected to the carry-out node of the FET transfer device, which selectively connects that node to either a drain potential when both inputs are unity or to ground potential when both inputs are zero, thereby efficiently generating the carry-out bit without regard for the state of the carry-in bit.

Abstract: Printer having a sheet feed and drum transport assembly, an exit assembly and at least one dryer. Various print parameters or conditions are monitored relating to the drying of the ink on print media. These print parameters include print data density, ink characteristics and ambient humidity. The monitored print parameters are used to control the drying. In addition the monitored print parameters are used to control the detaching of the print media from a rotary transport. In this manner, the printer approaches an optimization of the drying and detaching function with respect to time and energy.

Abstract: A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.

Abstract: A technique is disclosed for condensing the overall size of a PLA circuit and a number of circuit elements involved in carrying out a desired logical OR operation. This is done by preconditioning the product term in the AND array to be grounded and the source of the AND array elements to be connected to the positive potential, polarities which are opposite to those for the balance of the PLA circuit. Therefore, if the particular AND or search array term is selected by means of its gate going positive, the product term line output will rise in potential instead of falling. Since any search array element will have this effect in a column of elements, an OR logical function is performed in what is otherwise the AND array of the PLA. The resultant localized change in polarities achieves a significant reduction in the number of product term columns necessary to carry out an OR logical function in the conventional AND array of a PLA.