Abstract: In the fabrication of integrated circuits, a method is provided for forming recessed silicon dioxide isolation in integrated circuits in which the "bird's beak" problems associated with conventional silicon dioxide-silicon nitride composite masking structures is minimized. A conventional composite mask comprising a bottom layer of silicon dioxide and an upper layer of silicon nitride having a plurality of openings defining the regions in the silicon substrate which are to be thermally oxidized is formed on a silicon substrate. Recesses are then etched in the silicon substrate in registration with the openings in the composite mask. Then, the silicon dioxide layer is, in effect, over-etched to extend the openings in the silicon dioxide to greater lateral dimensions than the openings in the silicon nitride layer whereby the silicon nitride at the periphery of the openings is undercut.A layer of silicon is then deposited in the recesses covering the undercut portions of said silicon nitride layer.

Abstract: A connector for providing improved shielding of connections made in coaxial type wire is provided having a contact connected to the signal conductor of the coaxial wire located within a one piece insulator housing which completely surrounds the contact. An electrically conductive metallic coating is located on the entire outer surface of the insulator housing. The shield of the coaxial wire is connected to the electrically conductive metallic coating. A further metallic shield is folded around the metallic coated one piece insulator so as to provide a low resistance electrical path therebetween.

Abstract: This specification describes an associative memory decoder for a memory system in which the units in the memory system are reconfigurable both in size and in number. The decoder is designed to take an address for that memory system and address memory space in the memory system irrespective of the amount of storage in the system so that the decoder has to change as memory capacity is added or subtracted from the memory system.

Abstract: This specification describes arrays for performing logic functions which include circuitry for testing the arrays to see if the arrays will perform the logic functions that they were designed to perform. This circuitry eliminates the need for storing information as to logic functions performed by any particular array and allows a uniform testing sequence to be used in testing all the arrays.

Abstract: A transaction execution system includes a host data processing system having a multiple account data base and a plurality of transaction terminals in communication with the host. The terminals each include a keyboard, a display, document handling subsystems, a hardware control subsystem, a communication subsystem and a programmable control subsystem supervising the other subsystems. A user initiates a transaction request by inserting a card into one of the terminals. After reading acceptable account identification information from the card the terminal requests entry of a preassigned personal ID number through the keyboard. The ID number is encrypted by the terminal at least once and communicated to the host along with information read from the card and entered via the keyboard.

Abstract: A planar integrated circuit structure having a dielectrically isolated Schottky Barrier contact.The structure has pockets of silicon surrounded by isolating regions of silicon dioxide extending from a planar surface, the silicon dioxide regions and silicon pockets being substantially coplanar at said surface. A layer of dielectric material, such as silicon nitride or a composite of silicon nitride over silicon dioxide, covers the surface. There is at least one opening extending through the dielectric layer to a coincident silicon pocket; the opening has larger lateral dimensions than said pocket so as to expose the pocket and a portion of the silicon dioxide region surrounding the pocket. A metallic layer in this opening forms a Schottky Barrier contact with the exposed silicon.

Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

Abstract: A square-shaped electron beam is stepped from one predetermined position to another in a line-by-line scan to form a desired pattern on each chip of a semiconductor wafer to which the beam is applied. At each of the predetermined positions, the beam is on, off, or on for a portion of the time period at which the beam is disposed at the predetermined position. The beam also can be offset both along its direction of movement and perpendicular thereto at each of the predetermined positions. Control of this movement of the beam is obtained through utilizing a memory with no change being made in the memory if the predetermined position at the next line does not have any change from the predetermined position at the line along which the beam is moving.

Abstract: Disclosed is a semiconductor light emitting diode (LED) array in which "cross-talk" between adjacent diodes in the array is minimized. The disclosed LED arrays have an absorbing layer on the backside of the devices and/or a guard ring region surrounding each device in order to absorb spurious reflections within the semiconductor crystal. Disclosed also is a method of making improved light emitting diodes (LED's).

Abstract: A method of ion implantation into a semiconductor substrate which comprises forming a layer of an electrically insulative material, such as silicon dioxide, on the substrate over the region to be ion implanted. Then, a beam of ions having sufficient energy to pass through the layer of insulative material and to penetrate into the substrate is directed at a particular portion of the insulative layer. Before proceeding further, at least the upper half of the insulative layer, and preferably all of the upper portion of the insulative layer, in excess of a remaining thickness of 100A, is removed by etching. Then, the substrate is heated whereby the ions are driven further into the substrate to form the selected ion implanted region.

Abstract: Structure: An integrated circuit structure with full dielectric isolation comprising a supporting substrate having a planar surface of dielectric material and a semiconductor layer on said dielectric surface which forms a planar interface with the surface. Regions of oxidized silicon extend through the layer from said interface, surrounding and dielectrically isolating pockets of silicon in the layer; the oxidized silicon regions extend to the upper surface of the semiconductor layer where they are substantially co-planar with the silicon pockets. The devices of the integrated circuit are formed in said silicon pockets.

Abstract: An improved write circuit for a gas panel produces a sequence of alternating polarity write pulses that are superimposed on a sequence of half cycle pulses of the sustain waveform. Thus the accumulation of charges on the walls of a light-emmitting cell that is required for a write operation is produced by a sequence of write pulses, and each write pulse is lower in amplitude than is required for a single write pulse. The write pulses are progressively shifted ahead in phase to further improve the operation.

Abstract: A versatile readily serviced transaction terminal includes a credit card control mechanism, a user keyboard, a user display, a document handling system for cash and printed transaction statements, and a system for controlling terminal operation. The terminal receives a user credit card having a magnetic stripe with prerecorded account information, reads the account information, and then receives a user personal ID number through the keyboard. As an available option, the terminal may require a predetermined correspondence between the personal ID number and the account information. After any required correspondence is satisfied, the user is permitted to operate the keyboard to indicate a selected one of an unlimited range of possible transaction requests.

Abstract: This specification describes an orderly arrangement of input and output lines for a programmable logic array chip (PLA). In the arrangement, a plurality of parallel current conducting lines called rails are positioned on the chip along side the arrays of the PLA. The inputs and outputs of the arrays are selectively connected to individual rails so that the rails carry the input signals to the arrays from off the chip and take output signals of the arrays off the chip and to inputs of the arrays. The rails are selectively segmented so that each segment of a rail may be used as a path for an input and/or output signal without interfering with signals on other segments of the same rail.