Abstract: The device structure is a bi-polar transistor having a region of inert atoms located in the collector adjacent to the base-collector junction. Another embodiment of the invention is a complementary insulated gate field effect transistor (IGFET) structure having N and P channel IGFETs with regions of implanted ions beneath the source and drain of one or both transistors, and/or annular regions projecting inwardly from the surface that surround or separate the different types of IGFETs.

Abstract: A virtual memory system is described in which a set of conversion tables is used to translate an arbitrarily assigned programming designation called a virtual address into an actual main memory location called a real address. To avoid the necessity of translating the same address over and over again, a table called the Directory Look Aside Table (DLAT) retains current virtual to real address translations for use where particular virtual addresses are requested more than once. A counter is associated with the DLAT. Each time a translation is stored in the DLAT the present count in the counter is stored along side the translation. Each time the DLAT is invalidated the counter is stepped so that with each invalidation a new number is stored in the DLAT with the next translation. When a translation is read out of the DLAT the number stored with the translation is compared with the present number in the counter. If they do not match a No Compare signal is provided.

Abstract: An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.

Abstract: A substantially square N-type impurity distribution profile in a silicon substrate produces much superior dc and ac characteristics in PN junction devices than can be expected from the usual phosphorus distribution profile. Such a square profile is obtained by diffusion of arsenic in the silicon substrate. The sharper impurity gradient allows a relatively low surface concentration to be used for the device. This lower surface concentration relieves precipitation and dislocation problems.

Abstract: Apparatus for signalling the occurrence of a match between an address that is supplied to a control store and an address that is to be watched for in a data processing system that executes several instruction streams concurrently. The apparatus signals the occurrence of a storage accessing operation at a location that is uniquely identified only by a virtual address that is longer than the actual address used in accessing the store. Means is provided for comparing the actual address used in accessing the store with the corresponding portion of the complete address, and means is provided for recording the location of an address to be watched for in a particular frame of the store and for signalling a match that occurs in such a frame. The apparatus is useful for testing the operation of the data processing system by relating a recurring malfunction of the system to the execution of an instruction at the address that is watched for.

Abstract: A method using a chemically vapor deposited (CVD) insulator to form a substantially planar layer of insulative material atop a conductive pattern on the surface of a substrate. The invention also features the use of a photoresist both as a mask for forming apertures in an underlying insulating layer as well as a lift-off material for a subsequently deposited conductive layer.In the method, a first insulating layer is deposited atop the substrate. Photoresist is then deposited; the resist pattern is exposed and developed; and the insulator is etched to expose selected areas of the substrate. A conductive film, preferably metal, is then deposited in blanket fashion in such quantity as to achieve the same height as the first insulator within the exposed apertures. The resist is lifted off, thereby leaving metal in the exposed apertures only. The pattern at this point consists of a single level of a conductive pattern and the insulator pattern with gaps between the conductors and the insulator.

Abstract: A method is provided for generating electrical test patterns for testing functional AC parameters of integrated semiconductor circuits from the test patterns used for the more conventional testing of the DC parameters of such circuits. The AC parameters include such factors as rise time, fall time and circuit delays.Starting with a DC pattern known to be sufficient for the DC testing of the circuit to be tested, each increment of the DC pattern which comprises a plurality of parallel bilevel signals is applied to a corresponding plurality of input points in a standard of the circuit, preferably computer simulated. The resulting output is sensed at output points in the circuit standard. Then, one by one, the input signals in the applied increment are changed while the remainder of the signals are maintained at their original levels. When a change in one of the signals produces a corresponding change in the output, this is noted as path for AC testing.

Abstract: In the fabrication of integrated circuits, a method is provided for forming dielectrically isolated regions in a silicon substrate comprising initially introducing conductivity-determining impurities into the substrate to form at least one region of one-type conductivity at the surface of said substrate. Then, a mask comprising a composite of a bottom layer of silicon dioxide and a top layer of silicon nitride is formed over at least a portion of the surface of said introduced regions. The substrate is then subsequently thermally oxidized to an extent sufficient to form regions of recessed silicon dioxide abutting and thus laterally defining said region of one-type conductivity. In this manner, it is ensured that the recessed silicon dioxide will abut introduced region irrespective of the extent of the "bird's beak" normally associated with thermal oxidation utilizing silicon dioxide-silicon nitride masking.

Abstract: In integrated circuit fabrication a method is provided involving the utilization of the same positive photoresist layer to form two different masks used in two separate etching steps. A positive photoresist layer is formed on a substrate, and portions of the positive photoresist layer are selectively exposed and developed to form the photoresist mask having a pattern of openings therethrough exposing the underlying substrate. Then, the substrate exposed in these openings is etched to form the pattern of recesses in the substrate corresponding to the openings. Next, portions of the remaining photoresist layer respectively adjacent to openings in the photoresist layer are exposed and developed to laterally expand such openings, after which the substrate exposed in these expanded openings is etched whereby the portions of the recesses underlying the original openings are etched deeper than the portions of the recesses underlying the expanded portions of said openings. The result is a two-level recess pattern.

Abstract: An improved current switch circuit having an active load. The active load comprises a current source at the collectors of the switch transistors which generates a current which is less than the current generated by the current source at the emitters of the switch transistors. The active load also includes both means for supplying the current difference between said source currents as supplementary current to the emitter current source when the associated switch transistors are conductive as well as means for diverting the source current at the collectors of the switch transistors when they are non-conductive.Depending on the current generated by the current sources, the performance of the circuit can be selected to optimize power dissipation versus switching speed. The circuit utilizes a minimum number resistors, thereby using a minimum amount of semiconductor area and insuring lower power dissipation than is available with prior art circuits.

Abstract: An integrated circuit substrate surface, particularly a surface of electrically insulative material, having a pattern of elevated areas and a complementary pattern of unelevated areas is planarized by forming the photoresist pattern in registration with the pattern of unelevated areas, the photoresist pattern having narrower lateral dimensions than said elevated pattern whereby registration is facilitated, flowing the photoresist pattern to laterally expand the photoresist to cover and thereby mask the unelevated areas, and etching to lower the elevated area which remain uncovered by the photoresist.

Abstract: A method for making a circuit package which exhibits an excellent heat transfer path from a semiconductor chip or other heat generating device to the heat sink can or cover of the package. A heat conducting pad is placed in proximate relationship to either the heat sink or to a surface of the chip and is metallurgically bonded to the other. In one of the preferred embodiments a low melting point solder, such as indium or an alloy thereof, is metallurgically bonded to the inside of the heat sink cover in a limited central region thereof. The solder is then positioned adjacent the chip and reflowed to substantially fill in the gap between the solder and the chip, but with no stress between the chip and the solder. The assembly exhibits excellent heat transfer from the chip to the cover and any associated heat dissipating structures.

Abstract: This specification describes a convolutional code and apparatus for the correction of errors in differentially encoded quadrature phase shift keyed data (DQPSK). In each sequence of forty bits 24 are information bits and the remainder are parity bits. Two parity bits are generated for each three information bit set in the sequence in accordance with the following equations:P.sub.8.sup.a = i.sub.8.sup.a .sym.i.sub.8.sup.b .sym.i.sub.6.sup.b .sym.i.sub.1.sup.b .sym.i.sub.3.sup.c .sym.i.sub.2.sup.cP.sub.8.sup.b = i.sub.8.sup.a .sym.i.sub.6.sup.a .sym.i.sub.3.sup.a .sym.i.sub.5.sup.b .sym.i.sub.8.sup.c .sym.i.sub.4.sup.cwhere i.sub.8.sup.a, i.sub.8.sup.b and i.sub.8.sup.c are the three information bits in the set associated with the parity bits P.sub.8.sup.a and P.sub.8.sup.b while the other information bits are from the seven sets of the sequence preceding the set associated with the parity bits.

Abstract: A method for forming coplanar thin films, particularly conductor-insulator patterns, on a substrate. A pattern which includes a first thin film and an expendable material deposited thereon is formed on the substrate. The expendable material is selected so that it can be selectively removed by an etchant which does not attack the first thin film or an insulator which is to be deposited. The second thin film is deposited by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the second film. This results in the covering of the exposed substrate surfaces and the upper surface of the material with the second film but leaving the side surfaces of the material exposed. The expendable material is then chemically etched so as to lift-off both the material and the second film deposited thereon, thereby leaving a coplanar pattern of first and second thin films.

Abstract: A circuit package exhibiting an excellent heat transfer path from a semiconductor chip or other heat-generating device to the heat-sink can or cover of the package. A heat-conducting pad is metallurgically bonded to either said cover or a surface of said device; the pad is also separably attached, but metallurgically unbonded, to the other. In one preferred embodiment, a readily deformable metal or alloy, such as indium, is metallurgically bonded to a limited central region of the heat sink cover. The deformable metal is separably attached to a major surface of the chip so that there is no stress between the chip or its joints and the solder during the electrical operation of the chip when it generates heat. The preferred method of fabrication involves the mechanical deformation of a mass of solder against the back side of the chip, after the solder has been metallurgically bonded to heat sink.

Abstract: A thermal display comprising an array of semiconductor heater mesas having a larger cross-sectional area at the display surface than at the support surface. The preferred structure is in the shape of a truncated, inverted pyramid. The novel method includes forming the inverted heater elements by etching trenches in one surface of the semiconductor substrate and forming the heater mesas at the opposite surface, with the trenches defining the individual mesas.

Abstract: This specification describes a set of arrays for performing logic function in various subsets of the original set. The array structure is characterized by a plurality of arrays joined together with a bidirectional bussing system. This bussing system comprises addressing lines of the arrays joined together by switching circuitry used to regroup the set into subsets as necessary to perform the logic functions.

Abstract: An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor in a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction.

Abstract: A beam-lead integrated circuit chip structure which comprises a semiconductor chip substrate having a passivated planar surface from which active and passive devices in the circuit extend into the substrate. A plurality of peripheral beam-leads interconnected with the chip devices extend beyond the periphery of the chip and a plurality of solder mounds having a lower melting point than said beam-leads extends from the surface of the chip to a point beyond the plane of the beam-leads.This chip structure permits a method of automatic alignment of said plurality of beam-leads with a corresponding plurality of beam-leads on a dielectric substrate which involves placing the chip on the substrate so that said plurality of solder mounds are respectively in registration with a plurality of corresponding solder-wettable land pads on said non-wettable dielectric substrate.

Abstract: A printer responds to channel commands including coded data received over a channel from a data processing unit by printing characters represented by the coded data using an electrophotographic printing arrangement. The coded data received by the printer is first translated into corresponding graphic codes or addresses by a translate table employing a predetermined translation code, following which the addresses are used to locate sets of character image bits stored within a plurality of character generator modules. Each set of character image bits is used to modulate a laser scan of a printing drum to effect printing of desired characters. Both the translate table and the character generator modules are program alterable, and the data stored therein can be loaded directly from or changed in response to data and instructions from the data processing unit.