Abstract: This specification describes an associative memory cell capable of performing logic functions. The cell comprises two transistors with their collectors connected to an output line and their emitters connected to an input line carrying either the true or complement of one variable. The bases of the two transistors can each be selectively connected to either the true and complement of a second variable or fixed at one of two reference or logic levels to permit the performing of sixteen different logic functions of the two input variables by the cell.

Abstract: An improved operation is provided for a graphic tablet of the type in which a pen is capacitively coupled to sets of X dimension wires and Y dimension wires that are digitally activated to produce a pen signal that signifies the position of the pen on the tablet. Compensation is provided for variations in the pen signal that are attributable only to differences in the height of the pen above the tablet as the pen is operated over intervening layers of paper of various thicknesses. The drivers that activate the tablet are controlled to establish a sequence of different activation patterns and a corresponding sequence of analog pen signals. These signals are operated on to produce a pen position address that is substantially compensated for variations in pen height.

Abstract: This invention relates to a system for communicating between a central station, such as a host processor, and one or more remote stations, such as terminal devices, on a pair of communication loops. A remote station operates normally on a selected one of the loops (the primary loop for the station) and it has access to but does not normally use the other loop (the secondary loop for the station). An improved apparatus and method is provided for switching a remote station from its primary loop to its secondary loop when its primary loop is disabled. Means is provided for a remote station to listen to messages on its secondary loop. For switching the remote stations from a disabled primary loop, a unique command is transmitted on their secondary loop. Remote devices operating with a primary connection to the loop that carries this command recognize the command and respond in a non-interferring way.

Abstract: A method of planarizing an electrically insulative layer formed over a non-planar integrated circuit substrate having raised portions. After the electrically insulative layers are deposited over such substrate, the layer has elevations corresponding to the underlying raised portions of the substrate. A masking layer is formed on the electrically insulative layer having at least one opening therethrough coincident with an elevation in the insulative layer; this opening has smaller lateral dimensions than the coincident elevation, thereby facilitating alignment. The elevation in the insulative layer exposed in said at least one opening is then etched to the level of the unelevated portion of the layer, and the insulative layer is then resputtered for a period of time sufficient to planarize the remainder of such etched elevation to the level of the unelevated portions.

Abstract: In the fabrication of integrated circuits, a method is provided for forming masking structures comprising silicon nitride which avoids the stresses and dislocations associated with direct silicon nitride masking as well as the "bird's beak" problems associated with silicon dioxide-silicon nitride composite mask structures. The mask is formed by first forming a silicon dioxide mask having at least one opening through which the substrate is exposed. Then, a mask comprising silicon nitride is formed on the first mask; this mask has at least one opening laterally smaller than the openings in the first mask and respectively in registration with at least some of the openings in said first mask. Thus, the second mask contacts and covers a portion of the exposed silicon substrate under each of the registered openings.The masked silicon substrate is subjected to a processing step such as oxidation, etching or diffusion which alters the characteristics of those portions of the silicon substrate remaining exposed.

Abstract: A planar semiconductor integrated circuit chip structure comprising a surface from which a plurality of regions of different conductivity types extend into the chip to provide the transistors and resistors wherein said transistors and resistors are arranged in a plurality of repetitive cells, each of said cells containing a sufficient number of transistors and resistors to form a selected type of logic circuit. The cells are arranged in an orthogonal array with the cells in substantially parallel rows in both orthogonal directions. The structure includes a level of metallization disposed above and insulated from the array by at least one layer of electrically insulative material. This level of metallization comprises a plurality of groups of substantially parallel lines respectively disposed above and running parallel to a corresponding plurality of interfaces between rows of said cells in one of the orthogonal directions.

Abstract: A beam-lead integrated circuit chip structure which comprises a semiconductor chip substrate having a passivated planar surface from which active and passive devices in the circuit extend into the substrate. A plurality of peripheral beam-leads interconnected with the chip devices extend beyond the periphery of the chip and a plurality of solder mounds having a lower melting point than said beam-leads extends from the surface of the chip to a point beyond the plane of the beam-leads.This chip structure permits a method of automatic alignment of said plurality of beam-leads with a corresponding plurality of beam-leads on a dielectric substrate which involves placing the chip on the substrate so that said plurality of solder mounds are respectively in registration with a plurality of corresponding solder-wettable land pads on said non-wettable dielectric substrate.

Abstract: An improved tablet system is disclosed of the type having an array of X dimension wires and Y dimension wires that are capacitively coupled to a pen that a user holds to the tablet to produce a position signal. The X and Y wires are individually coupled to drivers so that the wires on one side of the pen position can be activated and the wires on the other side can be not activated for a pen position sensing operation. To reduce the number of drivers required for a large tablet, the wires are arranged in groups with an individual driver capacitively coupled to a correspondingly positioned wire in each group. A new packaging arrangement is provided and a new system is provided for addressing the drivers to produce the selected activation pattern.

Abstract: A novel Schottky Barrier structure which is integratable with standard integrated circuits comprising a metal layer of Al.sub.2 Pt in contact with a high resistivity semiconductor region. The structure is fabricated by first forming a platinum silicide layer on said silicon substrate and then applying a metallic layer comprising aluminum on said first layer, after which the structure is sintered at a temperature of at least 400.degree. C. for at least an hour.

Abstract: This specification describes means that permit the variation of circuits, particularly latch circuits, used in programmable logic array chips (PLAs). The latch circuits are changeable to enable the selection of one of three different latch configurations to be used or in combination on the same PLA chip. The differences in the circuit configurations of the different types of latches occur only in metallization pattern of the chip so that chips with different latch configurations can be manufactured with a minimum of different processing steps.

Abstract: A method for determining whether an integrated circuit chip containing a plurality of separable circuits is operable when one or more of the separable circuits is not functional.A chip including a plurality of discrete or separable circuits, each of which include means for selectively receiving and distributing a voltage level necessary to render the particular circuit operable, the chip further including a region of one type conductivity at said voltage level common to all of the discrete circuits is tested by a method which will insure that short-circuits between a particular circuit found not to be functional and therefore not to be rendered operable and the common region will not inadvertently apply the voltage level from the common region to voltage receiving and distribution means in the non-functional circuit.All the discrete circuits are first tested to determine which are functional.

Abstract: An improved tablet system is disclosed of the type having an array of X and Y dimension wires that are capacitively coupled to a pen that a user holds to the tablet to produce a position signal. Drivers are provided for individual wires to produce a selected activation pattern for the wires. The drivers are operated from a shift register and associated components that are mounted on the tablet and are connected to an associated processor through only a small number of conductors.

Abstract: A plurality of magnetic liquid streams is simultaneously excited to produce a plurality of streams of magnetic droplets of substantially uniform spacing and substantially uniform velocity. Each of the droplets in each of the streams passes over a separate selector for each stream to determine whether the droplet will be utilized for printing on a paper. A predetermined number of the droplets of each of the streams is subjected to a time periodic deflection to cause a first half of the predetermined number of droplets, which have been selected for printing by the selectors, to engage a paper in a first line and a second half to engage the paper in a second line. A ramp voltage deflection is separately applied to the predetermined number of droplets of each stream subjected to each half of the time periodic deflection to cause the print lines of the droplets to be orthogonal to the direction of movement of the paper.

Abstract: This specification describes a differential sense amplifier serving balanced sense lines. An imbalance in bias potential on the sense lines holds the sense amplifier in an insensitive state until just before data is to be read on the sense lines. Then a shunting device connected across the sense lines and across the inputs to the differential amplifier is activated to reduce the imbalance and thereby sensitize the differential amplifier. This shunting device is controlled by a feedback path that senses the biasing condition and shuts off the shunting device when the amplifier is in condition to perform the Read cycle.

Abstract: A positive resist image is produced by exposing, to radiation in a predetermined pattern, a polymeric material containing polymerized alkyl methacrylate units and polymerized monoethylenically unsaturated acid units. The exposed and unexposed areas are distinguished by their different respective abilities to be swelled in an appropriate swelling agent, and the swelled areas are removed by dispersal in a nonsolvent liquid.

Abstract: A planar semiconductor integrated circuit chip structure containing a planar surface from which a plurality of regions of different types and concentrations of conductivity-determining impurities extends into the chip to provide the active and passive devices of the circuit. The surface is passivated with an insulative structure containing at least two layers with a metallization pattern for interconnecting the integrated circuit devices formed on the first layer and via holes passing through the second or upper layer into contact with various portions of this metallization pattern. The via holes are arranged so that a majority of the holes are disposed above surface regions having such impurity types and concentrations that would form Schottky barrier contacts with the metal of contacts formed in said via holes.

Abstract: In integrated circuit fabrication, a method is provided for simultaneously forming two regions of the same conductivity-type such as the base and isolation regions. In one embodiment, an epitaxial layer of one conductivity-type is formed on a substrate of opposite conductivity-type, after which dopant ions of the opposite conductivity-type are introduced into the epitaxial surface areas which are to provide the base and isolation regions, and in addition, the isolation regions are bombarded with non-dopant ions having a maximum atomic number of two, e.g., hydrogen or helium ion while the base regions are appropriately masked and remain umbombarded, said bombardment is carried out at temperatures below 300.degree. C, preferably room temperature. The bombardment is preferably carried out so that the non-dopant ions are implanted primarily in regions below the isolation regions. Next, the wafer is heated at a temperature at a range of from 600.degree. - 900.degree.

Abstract: A method for use in forming thin film patterns in the fabrication of integrated circuits. The method involves depositing a bottom layer of positive photoresist material on a substrate, and forming over the bottom layer, a discrete light-transparent top layer of positive photoresist material which is less solubilized in developer after exposure to light than is the material in the bottom layer. The top and bottom layers are preferably separated by an intermediate layer of a light-transparent polymeric material which is immiscible in the bottom layer and unaffected by the subsequently applied top layer.The composite structure is exposed to a selected pattern of light, e.g., through a mask, and developer for the positive photoresist material is applied to the top and bottom layers. In the case where an intermediate layer is used, the top layer is developed first.

Abstract: A planar integrated semiconductor circuit master-slice structure in which the insulation layer over the planar surface remains intact and free of undesirable short-circuit paths in the area beneath excess "unused" contact terminals which are not part of the selected circuit configuration formed by a selected surface metallization pattern on the insulative layer which selectively interconnects less than all of the contact terminals with less than all of the components extending from the planar surface of a semiconductor substrate beneath the insulative layer.During D.C. sputter cleaning or etching utilized in the formation of the contact terminals and the metallization pattern, there is an undesirable charge accumulation on the unused contact terminals which tends to exceed the dielectric breakdown strength of the insulative layer beneath the terminal. This shorts the unused pad to the semiconductor substrate beneath the terminal.

Abstract: A three-dimensional magnetic bubble device formed by depositing, on a flexible substrate, a plurality of pseudo-chips of amorphous metallic film capable of supporting magnetic bubbles. These pseudo-chips are interconnected by thin-film conductors also deposited on the flexible substrate. The substrate is then folded, on itself, a number of times to produce a three-dimensional magnetic bubble device. Optionally, a low temperature lamination step can be employed to complete the process. The folding step or steps, result in a number of layers, to which a common rotating magnetic field may be applied for propagation purposes.