Abstract: A method for forming feedthrough connections, or via studs, between levels of metallization atop semiconductor substrates. A first level conductive pattern is formed atop the substrate. A feedthrough pattern is then formed atop the first conductive pattern, the feedthrough pattern including one or more metal studs and a second, expendable material disposed on the studs. The formation of the feedthrough pattern is preferably accomplished by a lift-off process. The expendable material is removable by an etchant which does not substantially attack either the metal or the substrate. An insulator is deposited atop the substrate and the pattern by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the insulator, thereby covering the exposed substrate surfaces and the expendable material but leaving the side surfaces of the material exposed.

Abstract: A thermally conducting cushion-like elastomeric pad of RTV (Room Temperature Vulcanized) silicone rubber moled with indentations in one surface to fit in glove-like relationship with electronic components situated on a component carrying card, the opposite surface mounted flush with a heat sink such that the heat generated by the electronic components is transferred through the pad to the heat sink.

Abstract: This specification describes a decoder for a programmable logic array (PLA) having opposite ends of input lines of the array connected to outputs of different decoders. Previously two-bit decoders were arranged on opposite sides of the array to generate input variables from two sets of two different input signals each and feed those input variables to four input lines. Here, instead of using two-bit decoders, four one-bit decoders are positioned on each side. The outputs of these one-bit decoders are programmable to change the connections between them and the input lines of the array. The arrangement permits the decoders to perform one-bit, two-bit decoding on signals on the same side of the input lines, to do two-bit decoding on signals on opposite sides of the array and in combination with other sets of decoders to do three and four-bit decoding of input signals.

Abstract: An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer.In the method for forming the field effect transistor, an impurity is introduced into the semiconductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact.

Abstract: A substantial increase in the reliability of metal-oxide-semiconductor field effect transistor (MOSFET) devices having a thin gate dielectric is achieved by providing a thin film of phosphosilicate glass (PSG) on the thin dielectric and completely covering the PSG layer with the gate metallization. The metallization extends over a thick film of phosphosilicate glass which is disposed on the thick insulator covering the source and drain regions.

Abstract: A method for forming monocrystalline silicon carbide on a silicon substrate by converting a portion of the monocrystalline silicon substrate into a porous silicon substance by anodic treatment carried out in an aqueous solution of hydrofluoric acid, heating the resultant substrate to a temperature in the range of 1050.degree. C to 1250.degree. C in an atmosphere that includes a hydrocarbon gas for a time sufficient to react the porous silicon and the gas, thereby forming a layer of monocrystalline silicon carbide on the silicon substrate.

Abstract: A substantial increase in the reliability of metal-oxide-semiconductor field effect transistor (MOSFET) devices having a thin gate dielectric is achieved by providing a thin film of phosphosilicate glass (PSG) on the thin dielectric and completely covering the PSG layer with the gate metallization. The metallization extends over a thick film of phosphosilicate glass which is disposed on the thick insulator covering the source and drain regions.

Abstract: This specification describes a decoder for use in a programmable logic array (PLA) of the type having opposite ends of input lines of the array connected to outputs of different decoders. Instead of using the outputs of two two-bit decoders to drive four input lines, as was previously done, four one-bit decoders are used to drive the four input lines. This arrangement permits the one-bit decoders with minor modifications to be used to perform four one-bit decodes of four input signals, two two-bit decodes on two sets of two input signals on either side of the array and one two-bit decode on two input signals that are on opposite sides of the array.

Abstract: This specification describes an associative memory cell capable of performing logic functions. The cell comprises two transistors with their collectors connected to an output line; with their emitters either left floating or connected to an input line carrying either true or complement of one variable; and with their bases either connected to an input line carrying the true or complement of a second variable or to the output line which is maintained at a fixed potential. This permits the performing of sixteen different logic functions of the two input variables by the cell.

Abstract: An integrated circuit chip carrier with multi-level metallurgy, in which the effects of the metallurgy in causing elevation irregularities at the various levels of the structure are minimized, is produced by a method wherein a first plurality of levels of metallization patterns respectively separated by layers of dielectric material are first formed on a planar primary layer supported on a temporary substrate having a chemical etchability different from that of the layer. The primary layer is electrically insulative with respect to said metallization patterns. Then, a supporting layer is formed on the uppermost covering layer, after which the substrate is removed with a chemical etchant which preferentially etches the substrate away from the insulative layer. Next, an opposite plurality of levels of metallization patterns are formed on the side of the insulative layer opposite to the first formed metallization patterns.

Abstract: This specification describes an apparatus for determining if more than one of n lines are up at a given time. The apparatus includes means for encoding the n lines into m lines where n = 2.sup.m. Two encoding signals are generated; one, X.sub.0 X.sub.1 . . . X.sub.m, complement of the other, Z.sub.0 Z.sub.1 . . . Z.sub.m. These two signals are Ex OR'd in accordance with the formula (X.sub.0 Z.sub.0) .sup.. (X.sub.1 Z.sub.1) . . . (X.sub.m Z.sub.m). If more than one line is up, the resultant of the Ex OR operation is one. Otherwise the resultant is zero.

Abstract: This hierarchical memory system has two memory units on each level. One of the units called the data store contains all the data at that level of the memory. The other unit called the copy back store contains all the changes that have been made in that data either by addition or modification. While the data store is interfaced with the next higher level in the hierarchical memory system or with the processing units for the data processing system, the second or copy back store can transfer the changes made in the data into the next lower level in the memory hierarchy system if the copy back store is free and the data store in the next lower level is not involved in transferring data up the hierarchy. The data store and the copy back data store in each level are on two different power systems and transfers of the changes to the next lower level are done in the order in which the change entered in the copy back store with the oldest entry being the first to be copied back.

Abstract: Two separate address lines are provided for each storage line of local storage. One address line is connected to a first group of bytes and the second address line is connected to the remaining bytes with each storage line containing the same addressing connection. Control circuits are provided for selecting any two address lines where the combination of the two provides access to both byte groups.

Abstract: A set of closely spaced, parallel conductive lines on an insulating support are located in face to face electrical contact with a corresponding set of conductive lines on a second insulating support, and a new structure is provided for adjusting the two sets of lines to match properly despite variations in the spacing between the lines of a set. The first set of lines has close, even, spacing. In the second set, the lines converge slightly from a spacing that is wider than the spacing of the first set to a spacing that is narrower than the spacing of the first set. During assembly, the position where contact occurs between the two sets is adjusted so that satisfactory electrical contact is made between each pair of lines.

Abstract: A circuit for supplying sustain voltage pulses to the orthogonal conductors of a gas display panel including voltage sensors to sense any change in sustain voltage amplitude with aging of the circuits and a voltage controlled oscillator to shift the operating frequency of sustain pulses as the amplitude changes. In that manner, the operating point of sustain voltage vs. frequency is shifted to take advantage of the slope in a graphical representation of sustain voltage margin to allow for shifting of the margin due to panel aging.

Abstract: A charge-coupled random access memory cell is formed in a semiconductor body divided into three adjacent regions. The first region has an impurity diffused therein and serves alternately as a source and a drain for charge carriers. The second or gate region has a threshold voltage determined by an impurity imparted thereto by either diffusion or ion implantation. The third or storage region has a lower threshold voltage than the gate region. A single unitary metal electrode extends in superimposed relation to the second and third regions. Upon the application of potentials to the first region and the electrode, charge carriers may be stored in or removed from the third region so as to write a "1" or a "0" in the cell.

Abstract: Apparatus for positioning a workpiece and tool in a precise location relative to each other by positioning in a predetermined site the workpiece, and then positioning the tool in a precise predetermined positon relative to the site in minimum total time. The apparatus comprises a closed loop position and velocity sensitive servo system connected to the workpiece, the servo system including positioning apparatus for positioning the workpiece in a predetermined site. A position indicator determines the actual position of the workpiece relative to a fixed reference and emits a signal output which is compared, in an error generator, with the desired position of the workpiece relative to the reference. The difference signal, from the error generator, is applied to the positioner and is used to bring the workpiece into the site. The positioner is provided with velocity feedback which cooperates with the positioning signal from the error generator to drive the workpiece into the predetermined site.

Abstract: In the bombardment of targets with beams of charged particles, a method for varying and controlling the diameter of such beams by passing the beam through an envelope of conductive material; the envelope is spaced from and coaxial with the beam. A selected D.C. potential is applied to the envelope, and the beam diameter is controlled by changing this applied potential in a direction away from ground potential to increase the beam diameter or by changing the potential in a direction toward ground potential to decrease said beam diameter.

Abstract: A charge-coupled random access memory cell is formed in a semiconductor body divided into three adjacent regions. The first region has an impurity diffused therein and serves alternately as a source and a drain for charge carriers. The second or gate region has a predetermined threshold voltage and the third or storage region has a lower threshold voltage. A single unitary metal electrode extends in superimposed relation to the second and third regions. Upon the application of potentials to the first region and the electrode, charge carriers may be stored in or removed from the third region so as to write a "1" or a "0" in the cell.

Abstract: In an ion implantation apparatus, a structure for measuring the beam current at the target wherein a Faraday Cage is formed by walls adjacent to and electrically insulated from the target in combination with the target, means for biasing the target at a negative potential, means for biasing the walls at ground potential and means for measuring the target current and the wall current and for combining the two to provide an accurate beam current measurement.